Victor Wanderley Costa de Medeiros

According to our database1, Victor Wanderley Costa de Medeiros authored at least 14 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Discrete controller synthesis applied to smart greenhouse.
Sustain. Comput. Informatics Syst., 2022

2021
Towards a control-as-a-service architecture for smart environments.
Simul. Model. Pract. Theory, 2021

2019
Random forest techniques for spatial interpolation of evapotranspiration data from Brazilian's Northeast.
Comput. Electron. Agric., 2019

2017
Análise de desempenho de Banco de Dados Relacionais e Não Relacionais em dados genômicos.
RITA, 2017

2016
A hardware accelerator for the alignment of multiple DNA sequences.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A hardware accelerator for the alignment of multiple DNA sequences in forensic identification.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
An inter-FPGA communication bus with error detection and dynamic clock phase adjustment.
J. Braz. Comput. Soc., 2015

Development of an educational application using HCD toolkit and open data on the recife culture.
Proceedings of the 14th Brazilian Symposium on Human Factors in Computing Systems, 2015

2012
FPGA-based architecture to speed-up scientific computation in seismic applications.
Int. J. High Perform. Syst. Archit., 2012

Energy Estimation Tool FPGA-based Approach for Petroleum Industry.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

2011

2009
Architecture for dense matrix multiplication on a high-performance reconfigurable system.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A Temporal Partitioning Methodology for Reconfigurable High Performance Computers.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008


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