Vladimir M. Ciric

Orcid: 0000-0002-1442-7959

According to our database1, Vladimir M. Ciric authored at least 15 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Extreme minority class detection in imbalanced data for network intrusion.
Comput. Secur., 2022

2020
Tiered Assignments in Lab Programming Sessions: Exploring Objective Effects on Students' Motivation and Performance.
IEEE Trans. Educ., 2020

2019
Cost Estimation of Blended Learning Course Delivery Through Public Cloud.
J. Univers. Comput. Sci., 2019

2016
All-Pairs Shortest Paths Algorithm for Regular 2D Mesh Topologies.
J. Univers. Comput. Sci., 2016

2015
Sparse Matrix Multiplication on Dataflow Engines.
Proceedings of the Parallel Processing and Applied Mathematics, 2015

2013
Tropical algebra based framework for error propagation analysis in systolic arrays.
Appl. Math. Comput., 2013

2012
Yield Modeling for Error Tolerant and Partially Defect Tolerant Arrays.
Proceedings of the IEEE 19th International Conference and Workshops on Engineering of Computer-Based Systems, 2012

2010
Yield analysis of partial defect tolerant bit-plane array.
Comput. Math. Appl., 2010

2008
Configurable folded array for FIR filtering.
J. Syst. Archit., 2008

Version control in project-based learning.
Comput. Educ., 2008

2007
Project-based learning environment for special purpose DSP architectures.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

Area-time tradeoffs in h.264/AVC deblocking filter design for mobile devices.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

2005
Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2002
Folded semi-systolic fir filter architecture with changeable folding Factor.
Neural Parallel Sci. Comput., 2002

Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002


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