Walter Guggenbühl

According to our database, Walter Guggenbühl authored at least 17 papers between 1987 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1995

Fast neural net simulation with a DSP processor array.

Urs A. Müller, Anton Gunzinger, Walter Guggenbühl

IEEE Trans. Neural Networks, 1995

1994

Switched-current memory circuits for high-precision applications.

Walter Guggenbühl, Jiandong Di, Josef Goette

IEEE J. Solid State Circuits, September, 1994

1993

Layout-dependent fault analysis and test synthesis for CMOS circuits.

Marcel Jacomet, Walter Guggenbühl

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

How to program and configure a heterogeneous multiprocessor.

Markus Zeltner, Bruno Schneuwly, Walter Guggenbühl

Mach. Vis. Appl., 1993

Neural net simulation with MUSIC.

Urs A. Müller, Anton Gunzinger, Walter Guggenbühl

Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

1992

Analog CMOS implementation of a multilayer perceptron with nonlinear synapses.

Jerzy B. Lont, Walter Guggenbühl

IEEE Trans. Neural Networks, 1992

Achieving supercomputer performane for neural net simulation with an array of digital signal processors.

Urs A. Müller, Bernhard Bäumle, Peter Kohler, Anton Gunzinger, Walter Guggenbühl

IEEE Micro, 1992

Achieving Super Computer Performance with a DSP Array Processor.

Anton Gunzinger, Urs A. Müller, Walter Scott, Bernhard Bäumle, Peter Kohler, Johann vonder Mühll, Florian Müller-Plathe, Wilfred F. van Gunsteren, Walter Guggenbühl

Proceedings of the Proceedings Supercomputing '92, 1992

Architecture and realization of a multi signal processor system.

Anton Gunzinger, Urs A. Müller, Walter Scott, Bernhard Bäumle, Peter Kohler, Walter Guggenbühl

Proceedings of the Application Specific Array Processors, 1992

1991

Simulation lossless symmetrical three conductor systems.

Walter Guggenbühl, Guy Morbach, Michael Schaller

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

3D Scene Acquisition by Motion Induced Stereo.

Peter Schaeren, Bruno Schneuwly, Walter Guggenbühl

Proceedings of the Mustererkennung 1991, 1991

1990

The synchronous dataflow machine: a computer architecture for real time image processing.

Anton Gunzinger, Severin Mathis, Walter Guggenbühl

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

SYDAMA II: A Heterogeneous Multiprocessor System for Real Time Image Processing.

D. Stokar, Anton Gunzinger, Walter Guggenbühl, Edi Hiltebrand, Severin Mathis, Peter Schaeren, Bruno Schneuwly, Markus Zeltner

Proceedings of the CONPAR 90, 1990

1989

The SYnchronous DAtaflow MAchine: Architecture and Performance.

Anton Gunzinger, Severin Mathis, Walter Guggenbühl

Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

1988

A reconfigurable systolic array for real-time image processing.

Anton Gunzinger, Severin Mathis, Walter Guggenbühl

Proceedings of the IEEE International Conference on Acoustics, 1988

Datenflussrechner zur Echtzeitbildverarbeitung: Anwendungen.

Anton Gunzinger, Severin Mathis, Walter Guggenbühl

Proceedings of the Mustererkennung 1988, 1988

1987

Datenflußrechner zur Echtzeitbildverarbeitung: Softwareentwicklungsumgebung.

Anton Gunzinger, Severin Mathis, Walter Guggenbühl

Proceedings of the Mustererkennung 1987, 9. DAGM-Symposium, Braunschweig, 29.9., 1987