Walter Guggenbühl

Affiliations:
  • Swiss Federal Institute of Technology, Zürich, Switzerland


According to our database1, Walter Guggenbühl authored at least 26 papers between 1979 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

1996
Cascode circuits for low-voltage and low-current applications.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995
Fast neural net simulation with a DSP processor array.
IEEE Trans. Neural Networks, 1995

1994
Switched-current memory circuits for high-precision applications.
IEEE J. Solid State Circuits, September, 1994

1993
Layout-dependent fault analysis and test synthesis for CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

How to program and configure a heterogeneous multiprocessor.
Mach. Vis. Appl., 1993

Image Processing on SYDAMA-2: Concept and Realization of the Software Environment.
Proceedings of the Parallel Computing: Trends and Applications, 1993

Neural net simulation with MUSIC.
Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

1992
Analog CMOS implementation of a multilayer perceptron with nonlinear synapses.
IEEE Trans. Neural Networks, 1992

Achieving supercomputer performane for neural net simulation with an array of digital signal processors.
IEEE Micro, 1992

Achieving Super Computer Performance with a DSP Array Processor.
Proceedings of the Proceedings Supercomputing '92, 1992

Architecture and realization of a multi signal processor system.
Proceedings of the Application Specific Array Processors, 1992

1991
Simulation lossless symmetrical three conductor systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

3D Scene Acquisition by Motion Induced Stereo.
Proceedings of the Mustererkennung 1991, 1991

1990
A voltage-controllable linear MOS transconductor using bias offset technique.
IEEE J. Solid State Circuits, February, 1990

A high-swing, high-impedance MOS cascode circuit.
IEEE J. Solid State Circuits, February, 1990

The synchronous dataflow machine: a computer architecture for real time image processing.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

SYDAMA II: A Heterogeneous Multiprocessor System for Real Time Image Processing.
Proceedings of the CONPAR 90, 1990

1989
Dummy transistor compensation of analog MOS switches.
IEEE J. Solid State Circuits, August, 1989

The SYnchronous DAtaflow MAchine: Architecture and Performance.
Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

1988
An analog trimming circuit based on a floating-gate device.
IEEE J. Solid State Circuits, December, 1988

A reconfigurable systolic array for real-time image processing.
Proceedings of the IEEE International Conference on Acoustics, 1988

Datenflussrechner zur Echtzeitbildverarbeitung: Anwendungen.
Proceedings of the Mustererkennung 1988, 1988

1987
Datenflußrechner zur Echtzeitbildverarbeitung: Softwareentwicklungsumgebung.
Proceedings of the Mustererkennung 1987, 9. DAGM-Symposium, Braunschweig, 29.9., 1987

1980
Distributed processing in industrial applications.
Euromicro Newsletter, 1980

1979
Interconnected small processors.
Euromicro Newsletter, 1979

Status report of microprocessing and microprogramming in Switzerland.
Euromicro Newsletter, 1979


  Loading...