Wang Kang

According to our database1, Wang Kang authored at least 47 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing.
IEEE Trans. Computers, 2019

Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems.
IEEE Access, 2019

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access, 2018

Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Data Management for Magnetic Racetrack Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

An Automatic Method for Semantic Focal Feature Point Tracking of 3D Human Model in Motion Sequence.
Proceedings of the 2018 International Conference on Cyberworlds, 2018

Process variation aware data management for magnetic skyrmions racetrack memory.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM.
IEEE Trans. on Circuits and Systems, 2017

Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective.
IEEE Trans. Computers, 2017

An Efficient Racetrack Memory-Based Processing-in-Memory Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Advanced Low Power Spintronic Memories beyond STT-MRAM.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Voltage-controlled MRAM for working memory: Perspectives and challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Ultrafast spintronic integrated circuits.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Skyrmion-Electronics: An Overview and Outlook.
Proceedings of the IEEE, 2016

Read disturbance issue and design techniques for nanoscale STT-MRAM.
Journal of Systems Architecture - Embedded Systems Design, 2016

Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A spin Hall effect-based multi-level cell for MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Evaluation of spin-Hall-assisted STT-MRAM for cache replacement.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Quantitative evaluation of reliability and performance for STT-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

PDS: pseudo-differential sensing scheme for STT-MRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. on Circuits and Systems, 2015

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
JETC, 2015

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Nonvolatile radiation hardened DICE latch.
Proceedings of the 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

Read disturbance issue for nanoscale STT-MRAM.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Novel Method: 3-D Gait Curve for Human Identification.
Proceedings of the Image and Graphics - 8th International Conference, 2015

2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distrib. Comput., 2014

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Spintronics for low-power computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An overview of spin-based integrated circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectronics Reliability, 2013

2012
Improving flash memory reliability with dynamic thresholds: Signal processing and coding schemes.
Proceedings of the 7th International Conference on Communications and Networking in China, 2012


  Loading...