Warren H. Debany Jr.

According to our database, Warren H. Debany Jr. authored at least 13 papers between 1991 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2008

Errata [corrections to "Modeling the Spread of Internet Worms Via Persistently Unpatched Hosts" (Mar/Apr 08 26-32)].

Warren H. Debany Jr.

IEEE Netw., 2008

Modeling the spread of internet worms via persistently unpatched hosts.

Warren H. Debany Jr.

IEEE Netw., 2008

2007

Line-of-sight networks.

Alan M. Frieze, Jon M. Kleinberg, R. Ravi, Warren Debany

Proceedings of the Eighteenth Annual ACM-SIAM Symposium on Discrete Algorithms, 2007

1996

Software Fault Tolerance Using Dynamically Reconfigurable FPGAs.

Kevin A. Kwiat, Warren Debany, Salim Hariri

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

Modeling a versatile FPGA for prototyping adaptive systems.

Kevin A. Kwiat, Warren H. Debany Jr., Salim Hariri

Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

1993

Coverage of Node Shorts Using Internal Access and Equivalence Classes.

Warren H. Debany Jr.

VLSI Design, 1993

A Method for Consistent Fault Coverage Reporting.

Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian

IEEE Des. Test Comput., 1993

1992

Effective concurrent test for a parallel-input multiplier using modulo 3.

Warren H. Debany Jr., Anthony R. Macera, Daniel Daskiewich, Mark Gorniak, Kevin A. Kwiat, Heather B. Dussault

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Empirical bounds on fault coverage loss due to LFSR aliasing.

Warren H. Debany Jr., Mark Gorniak, Daniel Daskiewich, Anthony R. Macera, Kevin A. Kwiat, Heather B. Dussault

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

Bounds on the sizes of irredundant test sets and sequences for combinational logic networks.

Warren H. Debany Jr., Carlos R. P. Hartmann

J. Electron. Test., 1991

Measuring the coverage of node shorts by internal access methods.

Warren H. Debany Jr.

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Design verification using logic tests.

Warren H. Debany Jr., Mark Gorniak, Anthony R. Macera, Kevin A. Kwiat, Heather B. Dussault, Daniel Daskiewich

Proceedings of the Second International Workshop on Rapid System Prototyping, 1991

Comparison of Random Test Vector Generation Strategies.

Warren H. Debany Jr., Carlos R. P. Hartmann, Pramod K. Varshney, Kishan G. Mehrotra

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991