Wei-Hao Chen

Orcid: 0000-0003-2079-8761

According to our database1, Wei-Hao Chen authored at least 36 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration.
Proceedings of the IEEE International Test Conference in Asia, 2023

2022
On-Chip Jitter Learning for PLL.
IEEE Des. Test, 2022

2021
Location-routing problem with time-dependent demands.
Comput. Ind. Eng., 2021

A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal.
Proceedings of the IEEE International Test Conference in Asia, 2021

2020
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter.
Proceedings of the IEEE International Test Conference, 2020

33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10<sup>-6</sup> Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Conditional Activation for Diverse Neurons in Heterogeneous Networks.
CoRR, 2018

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Efficient Key-Aggregate Proxy Re-Encryption for Secure Data Sharing in Clouds.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2018

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Pulse Rate Detection Method for Mouse Application Based on Multi-PPG Sensors.
Sensors, 2017

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
IEEE J. Solid State Circuits, 2017

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
IEEE J. Solid State Circuits, 2017

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Probabilistic Power Allocation for Cognitive Radio Networks With Outage Constraints and One-Bit Side Information.
IEEE Trans. Signal Process., 2016

Effective image forgery detection of tampered foreground or background image based on image watermarking and alpha mattes.
Multim. Tools Appl., 2016

2014
Outage-Constrained Coordinated Beamforming With Opportunistic Interference Cancellation.
IEEE Trans. Signal Process., 2014

Automatic assessment of affective episodes for daily activities analysis.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2014

2013
Effective forgery detection using DCT+SVD-based watermarking for region of interest in key frames of vision-based surveillance.
Int. J. Comput. Sci. Eng., 2013

Using swallow sound and surface electromyography to determine the severity of dysphagia in patients with myasthenia gravis.
Biomed. Signal Process. Control., 2013

2012
Robust image watermarking based on discrete wavelet transform-discrete cosine transform-singular value decomposition.
J. Electronic Imaging, 2012

Novel Detection of Image Forgery for Exchanged Foreground and Background Using Image Watermarking Based on Alpha Matte.
Proceedings of the 2012 Sixth International Conference on Genetic and Evolutionary Computing, 2012

2008
Channel Allocation for UMTS Multimedia Broadcasting and Multicasting.
IEEE Trans. Wirel. Commun., 2008

2003
Low-Power Embedded DSP Core for Communication Systems.
EURASIP J. Adv. Signal Process., 2003

An intelligent agent-based biomedical literature mining system for cancer-related genes.
Proceedings of the Fifth International Symposium on Multimedia Software Engineering, 2003


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