Wei-Yung Chen

According to our database¹, Wei-Yung Chen authored at least 2 papers in 2017.

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2017

A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017