Weiqiang Liu

Orcid: 0000-0001-8398-8648

Affiliations:
  • Nanjing University of Aeronautics and Astronautics, College of Electronic Information and Engineering, China


According to our database1, Weiqiang Liu authored at least 224 papers between 2010 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Untargeted Backdoor Attack Against Deep Neural Networks With Imperceptible Trigger.
IEEE Trans. Ind. Informatics, March, 2024

Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications.
IEEE Trans. Computers, February, 2024

An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA.
ACM Trans. Design Autom. Electr. Syst., January, 2024

2023
HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining.
IEEE Trans. Computers, December, 2023

Design of High Hardware Efficiency Approximate Floating-Point FFT Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Compression-resistant backdoor attack against deep neural networks.
Appl. Intell., September, 2023

Exact and Approximate Squarers for Error-Tolerant Applications.
IEEE Trans. Computers, July, 2023

Detecting backdoor in deep neural networks via intentional adversarial perturbations.
Inf. Sci., July, 2023

ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Dataset authorization control: protect the intellectual property of dataset via reversible feature space adversarial examples.
Appl. Intell., March, 2023

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Use the Spear as a Shield: An Adversarial Example Based Privacy-Preserving Technique Against Membership Inference Attacks.
IEEE Trans. Emerg. Top. Comput., 2023

AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption.
IEEE Trans. Emerg. Top. Comput., 2023

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.
IEEE Trans. Emerg. Top. Comput., 2023

Security and Approximation: Vulnerabilities in Approximation-Aware Testing.
IEEE Trans. Emerg. Top. Comput., 2023

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints.
IET Comput. Digit. Tech., 2023

Turn Passive to Active: A Survey on Active Intellectual Property Protection of Deep Learning Models.
CoRR, 2023

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Novel Method Against Hardware Trojans in Approximate Circuits.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Novel Intrinsic Physical Unclonable Function Design for Post-quantum Cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Towards a Lightweight CRYSTALS-Kyber in FPGAs: an Ultra-lightweight BRAM-free NTT Core.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

An Energy-efficient Approximate DCT Design for Image Processing (Invited).
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

An Efficient Hardware Accelerator of High-Speed NTT for CRYSTALS-Kyber Post-Quantum Cryptography.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A High-Performance SIKE Hardware Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction.
IEEE Trans. Emerg. Top. Comput., 2022

AxRMs: Approximate Recursive Multipliers Using High-Performance Building Blocks.
IEEE Trans. Emerg. Top. Comput., 2022

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers.
IEEE Trans. Emerg. Top. Comput., 2022

A Dynamically Configurable PUF and Dynamic Matching Authentication Protocol.
IEEE Trans. Emerg. Top. Comput., 2022

Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers.
IEEE Trans. Emerg. Top. Comput., 2022

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs.
IEEE Trans. Emerg. Top. Comput., 2022

One-to-N & N-to-One: Two Advanced Backdoor Attacks Against Deep Learning Models.
IEEE Trans. Dependable Secur. Comput., 2022

A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations.
IEEE Trans. Artif. Intell., 2022

A survey of approximate arithmetic circuits and blocks.
it Inf. Technol., 2022

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications.
IEEE Internet Things J., 2022

Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator.
IACR Cryptol. ePrint Arch., 2022

InFIP: An Explainable DNN Intellectual Property Protection Method based on Intrinsic Features.
CoRR, 2022

Imperceptible and Multi-channel Backdoor Attack against Deep Neural Networks.
CoRR, 2022

Compression-Resistant Backdoor Attack against Deep Neural Networks.
CoRR, 2022

PTB: Robust physical backdoor attacks against deep neural networks in real world.
Comput. Secur., 2022

Active intellectual property protection for deep neural networks through stealthy backdoor and users' identities authentication.
Appl. Intell., 2022

A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based Cryptosystems.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Low-cost stochastic number generator based on MRAM for stochastic computing.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A High-Speed CNN Hardware Accelerator with Regular Pruning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Lightweight and Efficient Schoolbook Polynomial Multiplier for Saber.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Lightweight and Efficient Hardware Implementation for Saber Using NTT Multiplication.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Better Security Estimates for Approximate, IoT-Friendly R-LWE Cryptosystems.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Sample-Specific Backdoor based Active Intellectual Property Protection for Deep Neural Networks.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications.
Proceedings of the Approximate Computing, 2022

An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits.
Proceedings of the Approximate Computing, 2022

Approximate Computing for Cryptography.
Proceedings of the Approximate Computing, 2022

Security Vulnerabilities and Countermeasures for Approximate Circuits.
Proceedings of the Approximate Computing, 2022

Approximate Arithmetic Circuits: Design and Applications.
Proceedings of the Approximate Computing, 2022

2021
AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication.
J. Signal Process. Syst., 2021

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.
IEEE Trans. Sustain. Comput., 2021

APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations.
IEEE Trans. Inf. Forensics Secur., 2021

Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers.
IEEE Trans. Emerg. Top. Comput., 2021

Reduced Precision Redundancy for Reliable Processing of Data.
IEEE Trans. Emerg. Top. Comput., 2021

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation.
IEEE Trans. Emerg. Top. Comput., 2021

AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

BCD Adder Designs Based on Three-Input XOR and Majority Gates.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Stochastic Dividers for Low Latency Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Backdoors hidden in facial features: a novel invisible backdoor attack against face recognition systems.
Peer-to-Peer Netw. Appl., 2021

A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning.
IEEE Open J. Comput. Soc., 2021

A lightweight key renewal scheme based authentication protocol with configurable RO PUF for clustered sensor networks.
Microelectron. J., 2021

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs.
J. Cryptogr. Eng., 2021

NaturalAE: Natural and robust physical adversarial examples for object detectors.
J. Inf. Secur. Appl., 2021

SocialGuard: An adversarial example based privacy-preserving technique for social images.
J. Inf. Secur. Appl., 2021

Protect the Intellectual Property of Dataset against Unauthorized Use.
CoRR, 2021

Protecting the Intellectual Properties of Deep Neural Networks with an Additional Class and Steganographic Images.
CoRR, 2021

ActiveGuard: An Active DNN IP Protection Technique via Adversarial Examples.
CoRR, 2021

Robust Backdoor Attacks against Deep Neural Networks in Real Physical World.
Proceedings of the 20th IEEE International Conference on Trust, 2021

Dynamically Configurable Physical Unclonable Function based on RRAM Crossbar.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Detect and Remove Watermark in Deep Neural Networks via Generative Adversarial Networks.
Proceedings of the Information Security - 24th International Conference, 2021

Design of An Approximate FFT Processor Based on Approximate Complex Multipliers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 2-Then-1 Bit/Cycle Asynchronous SAR ADC with Background Offset Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-Performance Systolic Array Montgomery Multiplier for SIKE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

DNN Intellectual Property Protection: Taxonomy, Attacks and Evaluations (Invited Paper).
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

GOMIL: Global Optimization of Multiplier by Integer Linear Programming.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance.
IEEE Trans. Emerg. Top. Comput., 2020

An Efficient and Parallel R-LWE Cryptoprocessor.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Hybrid Low Radix Encoding-Based Approximate Booth Multipliers.
IEEE Trans. Circuits Syst., 2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.
IEEE Trans. Circuits Syst., 2020

Profile-Based Output Error Compensation for Approximate Arithmetic Circuits.
IEEE Trans. Circuits Syst., 2020

Mathematical Modeling Analysis of Strong Physical Unclonable Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

High Performance Modular Multiplication for SIDH.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots.
Secur. Commun. Networks, 2020

Approximate Computing: From Circuits to Applications [Scanning the Issue].
Proc. IEEE, 2020

A Retrospective and Prospective View of Approximate Computing [Point of View}.
Proc. IEEE, 2020

Scanning the Issue.
Proc. IEEE, 2020

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.
Proc. IEEE, 2020

Ten years of hardware Trojans: a survey from the attacker's perspective.
IET Comput. Digit. Tech., 2020

Design, evaluation and application of approximate-truncated Booth multipliers.
IET Circuits Devices Syst., 2020

3D Invisible Cloak.
CoRR, 2020

Use the Spear as a Shield: A Novel Adversarial Example based Privacy-Preserving Technique against Membership Inference Attacks.
CoRR, 2020

Robust and Natural Physical Adversarial Examples for Object Detectors.
CoRR, 2020

DNN Intellectual Property Protection: Taxonomy, Methods, Attack Resistance, and Evaluations.
CoRR, 2020

LOPA: A linear offset based poisoning attack method against adaptive fingerprint authentication system.
Comput. Secur., 2020

Machine Learning Security: Threats, Countermeasures, and Evaluations.
IEEE Access, 2020

Active DNN IP Protection: A Novel User Fingerprint Management and DNN Authorization Control Technique.
Proceedings of the 19th IEEE International Conference on Trust, 2020

Transformer PUF : A Highly Flexible Configurable RO PUF Based on FPGA.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

A Novel Feature Extraction Strategy for Hardware Trojan Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

DC-LSTM: Deep Compressed LSTM with Low Bit-Width and Structured Matrices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Design and Implementation of an Approximate Softmax Layer for Deep Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Programmable Ring Oscillator PUF Based on Switch Matrix.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Security Analysis of Hardware Trojans on Approximate Circuits.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Efficient Hardware Generator for Massive Non-Stationary Fading Channels.
Proceedings of the IEEE Globecom Workshops, 2020

Embedding Backdoors as the Facial Features: Invisible Backdoor Attacks Against Face Recognition Systems.
Proceedings of the ACM TUR-C'20: ACM Turing Celebration Conference, 2020

2019
Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2019

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security.
ACM Trans. Embed. Comput. Syst., 2019

New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman.
IEEE Trans. Computers, 2019

Design and Analysis of Approximate Redundant Binary Multipliers.
IEEE Trans. Computers, 2019

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations.
IEEE Trans. Computers, 2019

Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs.
IET Comput. Digit. Tech., 2019

High-performance approximate half and full adder cells using NAND logic gate.
IEICE Electron. Express, 2019

Lattice-based Cryptography for IoT in A Quantum World: Are We Ready?
IACR Cryptol. ePrint Arch., 2019

Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method.
IEEE Access, 2019

Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Theoretical Analysis of Configurable RO PUFs and Strategies to Enhance Security.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Dynamic Reconfigurable PUFs Based on FPGA.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

An Improved Automatic Hardware Trojan Generation Platform.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Multi-Incentive Delay-Based (MID) PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

Security Analysis and Modeling Attacks on Duty Cycle Multiplexer PUF.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications.
J. Signal Process. Syst., 2018

Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders.
J. Signal Process. Syst., 2018

Design, Evaluation and Application of Approximate High-Radix Dividers.
IEEE Trans. Multi Scale Comput. Syst., 2018

Data Compression Device Based on Modified LZ4 Algorithm.
IEEE Trans. Consumer Electron., 2018

Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design.
IEEE Access, 2018

A Co-training Based Hardware Trojan Detection Technique by Exploiting Unlabeled ICs and Inaccurate Simulation Models.
Proceedings of the 17th IEEE International Conference On Trust, 2018

A Probabilistic Error Model and Framework for Approximate Booth Multipliers.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design of Majority Logic (ML) Based Approximate Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Optimization of Modular Multiplication for SIDH.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design of Approximate FFT with Bit-width Selection Algorithms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Application of an Approximate 2-D Convolver with Error Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Modelling Attack Analysis of Configurable Ring Oscillator (CRO) PUF Designs.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Design of Dynamic Range Approximate Logarithmic Multipliers.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A machine learning attack resistant multi-PUF design on FPGA.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Approximate Computing and Its Application to Hardware Security.
Proceedings of the Cyber-Physical Systems Security., 2018

2017
Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).
IEEE Trans. Multi Scale Comput. Syst., 2017

Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing.
IEEE Trans. Emerg. Top. Comput., 2017

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.
IEEE Trans. Computers, 2017

High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes.
IEEE Trans. Computers, 2017

Design and operational assessment of an intra-cell hybrid L2 cache.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

XOR gate based low-cost configurable RO PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of Approximate Logarithmic Multipliers.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

DC MUX PUF: A highly reliable feed-back MUX PUF based on measuring duty cycle.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Multiprecision Multiplication on ARMv8.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016
Design and Analysis of Inexact Floating-Point Adders.
IEEE Trans. Computers, 2016

A Modified Partial Product Generator for Redundant Binary Multipliers.
IEEE Trans. Computers, 2016

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications.
IEEE Trans. Computers, 2016

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

A fully parallel approximate CORDIC design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design of approximate Redundant Binary multipliers.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design and Performance Evaluation of Approximate Floating-Point Multipliers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and evaluation of an approximate Wallace-Booth multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low-cost configurable ring oscillator PUF with improved uniqueness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: An automatic evaluation platform for physical unclonable function test.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
Improving RO PUF design using frequency distribution characteristics.
IEICE Electron. Express, 2015

Design of 3-D quantum-dot cellular automata adders.
IEICE Electron. Express, 2015

RO PUF design in FPGAs with new comparison strategies.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Security Issues in QCA Circuit Design - Power Analysis Attacks.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

2013
QCA Systolic Array Design.
IEEE Trans. Computers, 2013

Power analysis attack of QCA circuits: A case study of the Serpent cipher.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Cost-efficient decimal adder design in Quantum-dot cellular automata.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A review of QCA adders and metrics.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Design rules for Quantum-dot Cellular Automata.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
QCA Systolic Matrix Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010


  Loading...