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Xin Jiang

Affiliations:
  • National Institute of Technology, Kitakyushu College, Kitakyushu, Japan
  • Waseda University, Graduate School of Information, Production and Systems, Japan


According to our database1, Xin Jiang authored at least 14 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2019
A Traffic-Robust Routing Algorithm for Network-on-Chip Systems.
[BibTeX]
[DOI]
Siying Xu
,
Michael Conrad Meyer
,
Xin Jiang
,
Takahiro Watanabe
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip.
[BibTeX]
[DOI]
Yaoying Luo
,
Michael Conrad Meyer
,
Xin Jiang
,
Takahiro Watanabe
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Low-Cost Congestion Detection Mechanism for Networks-on-Chip.
[BibTeX]
[DOI]
Zhengqian Han
,
Michael Conrad Meyer
,
Xin Jiang
,
Takahiro Watanabe
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

2018
PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs.
[BibTeX]
[DOI]
Jindun Dai
,
Renjie Li
,
Xin Jiang
,
Takahiro Watanabe
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017
High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem.
[BibTeX]
[DOI]
Xin Jiang
,
Xiangyang Lei
,
Lian Zeng
,
Takahiro Watanabe
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips.
[BibTeX]
[DOI]
Jindun Dai
,
Xin Jiang
,
Renjie Li
,
Takahiro Watanabe
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC.
[BibTeX]
[DOI]
Xin Jiang
,
Xiangyang Lei
,
Lian Zeng
,
Takahiro Watanabe
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Hybrid path-diversity-dominant output selection method for Network-on-Chip systems.
[BibTeX]
[DOI]
Jindun Dai
,
Wenda Ma
,
Xin Jiang
,
Takahiro Watanabe
Proceedings of the International SoC Design Conference, 2017

An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip.
[BibTeX]
[DOI]
Jindun Dai
,
Xin Jiang
,
Takahiro Watanabe
Proceedings of the International Conference on Computer, 2017

2016
An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip.
[BibTeX]
[DOI]
Lian Zeng
,
Tieyuan Pan
,
Xin Jiang
,
Takahiro Watanabe
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015
A Performance Enhanced Dual-switch Network-on-chip Architecture.
[BibTeX]
[DOI]
Lian Zeng
,
Xin Jiang
,
Takahiro Watanabe
IPSJ Trans. Syst. LSI Des. Methodol., 2015

2014
A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency.
[BibTeX]
[DOI]
Xin Jiang
,
Lian Zeng
,
Takahiro Watanabe
IPSJ Trans. Syst. LSI Des. Methodol., 2014

2013
An Efficient Algorithm for 3D NoC Architecture Optimization.
[BibTeX]
[DOI]
Xin Jiang
,
Ran Zhang
,
Takahiro Watanabe
IPSJ Trans. Syst. LSI Des. Methodol., 2013

2011
An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power.
[BibTeX]
[DOI]
Xin Jiang
,
Ran Zhang
,
Takahiro Watanabe
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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