Y. Arayashiki

According to our database, Y. Arayashiki authored at least 2 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (> 300 Layers) 3D Flash Memory.

N. Ishihara, Y. Shimada, T. Ochi, S. Seto, H. Matsuo, H. Yamashita, S. Morita, M. Ukishima, K. Uejima, Y. Arayashiki, S. Kajiwara, A. Murayama, K. Nishiyama, K. Sugimae, S. Mori, Y. Saito, T. Shundo, A. Maeda, H. Kamiya, Y. Uchiyama, M. Fujiwara, F. Aiso, K. Sekine, N. Ohtani

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory.

T. Morooka, T. Ishikawa, M. Komura, T. Kato, Y. Koyama, Y. Han, Y. Sugawara, D. Kuwabara, Y. Arayashiki, A. Murayama, K. Nishiyama, K. Sugimae, T. Ogura, H. Takeda, N. Kariya, Y. Goki, S. Konuma, Y. Kamiya, H. Yamashita, H. Shiga, K. Itagaki, R. Tanaka, T. Maeda, N. Ohtani, M. Fujiwara

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022