Y. K. Chong

According to our database, Y. K. Chong authored at least 4 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology.

R. Mathur, R. Sisodia, A. Chen, A. Singh, S. Thyagarajan, A. Cubeta, C. Andrieux, A. Sowden, Y. K. Chong

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022

5GHz SRAM for High-Performance Compute Platform in 5nm CMOS.

R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2019

A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms.

Cagla Cakir, Andy W. Chen, Y. K. Chong, Sriram Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, Mudit Bhargava

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2014

Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques.

Mudit Bhargava, Y. K. Chong, Vincent Schuppe, Bikas Maiti, Martin Kinkade, Hsin-Yu Chen, Andy W. Chen, Sanjay Mangal, Jacek Wiatrowski, Gerald Gouya, Abhishek Baradia, Sriram Thyagarajan, Gus Yeung

Proceedings of the Symposium on VLSI Circuits, 2014