Vivek Asthana

According to our database, Vivek Asthana authored at least 5 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

5GHz SRAM for High-Performance Compute Platform in 5nm CMOS.

R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2020

0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications.

Vivek Asthana, M. Jagadesh Kumar, Ayush Kulshrestha, Munish Kumar, Saikat Kumar Banik, Shruti Aggarwal

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2014

Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor.

Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology.

Vivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy

Proceedings of 2013 International Conference on IC Design & Technology, 2013

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.

Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy

Proceedings of the ESSCIRC 2013, 2013