Yasuo Iizuka

According to our database, Yasuo Iizuka authored at least 4 papers between 1994 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

A 45nm single-chip application-and-baseband processor using an intermittent operation technique.

Motoyasu Shirasaki, Yusaku Miyazaki, Masahiro Hoshaku, Hiroo Yamamoto, Sachio Ogawa, Takuya Arimura, Hiroshi Hirai, Yasuo Iizuka, Tsutomu Sekibe, Yoichi Nishida, Toshiyuki Ishioka, Junji Michiyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

1999

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine.

Shun-ichi Kurohmaru, Masatoshi Matsuo, Hiromasa Nakajima, Y. Kohashi, Tomonori Yonezawa, Toshihiro Mori-iwa, Masahiro Ohashi, M. Toujima, Tsuyoshi Nakamura, Mana Hamada, Takashi Hashimoto, H. Fujimoto, Yasuo Iizuka, Junji Michiyama, H. Komori

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

A DSP for DCT-based and wavelet-based video codecs for consumer applications.

Kiyoshi Okamoto, Takuya Jinbo, Toshiyuki Araki, Yasuo Iizuka, Hiromasa Nakajima, Minoru Takahata, Hisashi Inoue, Shun-ichi Kurohmaru, Tomonori Yonezawa, Kunitoshi Aono

IEEE J. Solid State Circuits, 1997

1994

Architectural design of a bi-level image high speed codec.

Hitoshi Horie, Tohru Ozaki, Hideyuki Shirai, Yasuo Iizuka

IEEE Trans. Circuits Syst. Video Technol., 1994