Yasuro Shobatake

According to our database, Yasuro Shobatake authored at least 5 papers between 1986 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Toshiba's Flow Attribute Notification Protocol (FANP) Specification.

Kenichi Nagami, Yasuhiro Katsube, Yasuro Shobatake, Akiyoshi Mogi, Shigeo Matsuzawa, Tatsuya Jinmei, Hiroshi Esaki

RFC, April, 1997

1991

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network.

Kenji Sakaue, Yasuro Shobatake, Masahiko Motoyama, Yoshinari Kumaki, Satoru Takatsuka, Shigeru Tanaka, Hiroyuki Hara, Kouji Matsuda, Shuji Kitaoka, Makoto Noda, Youichiro Niitsu, Masayuki Norishima, Hiroshi Momose, Kenji Maeguchi, Manabu Ishibe, Shoichi Shimizu, Toshikazu Kodama

IEEE J. Solid State Circuits, August, 1991

A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture.

Yasuro Shobatake, Masahiko Motoyama, Emiko Shobatake, Takashi Kamitake, Shoichi Shimizu, Makoto Noda, Kenji Sakaue

IEEE J. Sel. Areas Commun., 1991

1989

A prolog machine based on vlsi algorithms.

Yasuro Shobatake, Hideo Aiso

Syst. Comput. Jpn., 1989

1986

A Unification Processor Based on a Uniformly Structured Cellular Hardware.

Yasuro Shobatake, Hideo Aiso

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986