Yehua Ling

According to our database, Yehua Ling authored at least 10 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs.

Yu Zhang, Yi Zheng, Yehua Ling, Haitao Meng, Gang Chen

J. Syst. Archit., October, 2023

An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA.

Yuanxing Yan, Yehua Ling, Kai Huang, Gang Chen

J. Syst. Archit., March, 2023

Dense Depth Estimation for Monocular Endoscope Robot with an Adaptive Baseline.

Rihui Song, Zhidong Tan, Hongli Liang, Yehua Ling, Gang Chen, Kai Huang, Jin Gong

Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2023

Real-Time Instance Segmentation and Tip Detection for Neuroendoscopic Surgical Instruments.

Rihui Song, Silu Guo, Ni Liu, Yehua Ling, Jin Gong, Kai Huang

Proceedings of the Neural Information Processing - 30th International Conference, 2023

Accelerated Optimization for Simulation of Brain Spiking Neural Network on GPGPUs.

Fangzhou Zhang, Mingyue Cui, Jiakang Zhang, Yehua Ling, Han Liu, Kai Huang

Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

2022

Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network.

Yehua Ling, Tao He, Yu Zhang, Haitao Meng, Kai Huang, Gang Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA.

Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

FlowAcc: Real-Time High-Accuracy DNN-based Optical Flow Accelerator in FPGA.

Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Hardware accelerator for an accurate local stereo matching algorithm using binary neural network.

Yehua Ling, Tao He, Haitao Meng, Yu Zhang, Gang Chen

J. Syst. Archit., 2021

2020

StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network.

Gang Chen, Yehua Ling, Tao He, Haitao Meng, Shengyu He, Yu Zhang, Kai Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020