Yehua Ling

Orcid: 0000-0002-1196-6615

According to our database1, Yehua Ling authored at least 16 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Self-Attention-Based LiDAR Point Cloud Compression Framework in Autonomous Driving Environments.
IEEE Trans. Ind. Informatics, June, 2026

UECNet: A unified framework for exposure correction utilizing region-level prompts.
Knowl. Based Syst., 2026

Domain adaptive object detection via CLIP-space guidance and LoRA fine-tuning.
Expert Syst. Appl., 2026

2025
GAEM: Graph-Driven Attention-Based Entropy Model for LiDAR Point Cloud Compression.
IEEE Trans. Circuits Syst. Video Technol., September, 2025

DAPCC: Diverse Attention-Based Entropy Model for Dynamic LiDAR Point Cloud Compression.
IEEE Trans. Geosci. Remote. Sens., 2025

2024
An End-to-End ConvLSTM-based Method for Point Cloud Streaming Compression.
Proceedings of the International Conference on Advanced Robotics and Mechatronics, 2024

2023
A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs.
J. Syst. Archit., October, 2023

An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA.
J. Syst. Archit., March, 2023

Dense Depth Estimation for Monocular Endoscope Robot with an Adaptive Baseline.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2023

Real-Time Instance Segmentation and Tip Detection for Neuroendoscopic Surgical Instruments.
Proceedings of the Neural Information Processing - 30th International Conference, 2023

Accelerated Optimization for Simulation of Brain Spiking Neural Network on GPGPUs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

2022
Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

FlowAcc: Real-Time High-Accuracy DNN-based Optical Flow Accelerator in FPGA.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Hardware accelerator for an accurate local stereo matching algorithm using binary neural network.
J. Syst. Archit., 2021

2020
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020


  Loading...