Yemin Dong
Orcid: 0000-0002-4277-5547
According to our database1,
Yemin Dong
authored at least 12 papers
between 2018 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
A calibration scheme for SAR ADCs based on capacitor weight optimization using an improved simulated annealing algorithm.
Microelectron. J., 2025
Microelectron. J., 2025
Area and timing optimized 8B/10B pretreating and decoding circuit for JESD204B controller.
IEICE Electron. Express, 2025
A 0.75 <i>µ</i>A-quiescent current, output capacitor-less LDO regulator with high power supply rejection.
IEICE Electron. Express, 2025
2024
An all-digital low-complexity blind background calibration of timing mismatch in time-interleaved ADCs.
Microelectron. J., 2024
2023
A fast-convergence, tree-structured, fully-parallel digital background timing mismatch calibration method for four-channel TIADC based on perfect reconstruction filter bank.
Microelectron. J., November, 2023
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
2020
Design of a High-Performance Low-Cost Radiation-Hardened Phase-Locked Loop for Space Application.
IEEE Trans. Aerosp. Electron. Syst., 2020
IEICE Trans. Electron., 2020
A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration.
IEICE Electron. Express, 2020
A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure.
IEICE Electron. Express, 2020
2018
IEICE Electron. Express, 2018