Yibin Yang

Orcid: 0000-0001-6062-3531

Affiliations:
  • Georgia Institute of Technology, Atlanta, GA, USA


According to our database1, Yibin Yang authored at least 12 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Tight ZK CPU: Batched ZK Branching with Cost Proportional to Evaluated Instruction.
IACR Cryptol. ePrint Arch., 2024

Toward Malicious Constant-Rate 2PC via Arithmetic Garbling.
IACR Cryptol. ePrint Arch., 2024

Programmable Payment Channels.
Proceedings of the Applied Cryptography and Network Security, 2024

2023
Towards Generic MPC Compilers via Variable Instruction Set Architectures (VISAs).
IACR Cryptol. ePrint Arch., 2023

Off-Chain Programmability at Scale.
IACR Cryptol. ePrint Arch., 2023

Batchman and Robin: Batched and Non-batched Branching for Interactive ZK.
IACR Cryptol. ePrint Arch., 2023

Two Shuffles Make a RAM: Improved Constant Overhead Zero Knowledge RAM.
IACR Cryptol. ePrint Arch., 2023

Scalable Off-Chain Auctions.
IACR Cryptol. ePrint Arch., 2023

2022
EZEE: Epoch Parallel Zero Knowledge for ANSI C.
IACR Cryptol. ePrint Arch., 2022

Just How Fair is an Unreactive World?
IACR Cryptol. ePrint Arch., 2022

Zero Knowledge for Everything and Everyone: Fast ZK Processor with Cached RAM for ANSI C Programs.
IACR Cryptol. ePrint Arch., 2022

2021
Zero Knowledge for Everything and Everyone: Fast ZK Processor with Cached ORAM for ANSI C Programs.
Proceedings of the 42nd IEEE Symposium on Security and Privacy, 2021


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