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Yilong Liao

Orcid: 0000-0003-3684-868X

According to our database1, Yilong Liao authored at least 5 papers between 2017 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process.
[BibTeX]
[DOI]
Yupeng Fu
,
Lianming Li
,
Yilong Liao
,
Xuan Wang
,
Yongjian Shi
,
Dongming Wang
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Influence of LFSR Dither on the Periods of a MASH Digital Delta-Sigma Modulator.
[BibTeX]
[DOI]
Yilong Liao
,
Xiangning Fan
,
Zaijun Hua
IEEE Trans. Circuits Syst. II Express Briefs, 2019

MASH DDSM with Negative Feedback.
[BibTeX]
[DOI]
Yilong Liao
,
Xiangning Fan
,
Zaijun Hua
J. Circuits Syst. Comput., 2019

2017
Spur-Free MASH DDSM with Eliminable Dither.
[BibTeX]
[DOI]
Yilong Liao
,
Xiangning Fan
Proceedings of the Wired/Wireless Internet Communications, 2017

Spur-Free and Stable Digital Delta-Sigma Modulator via Using HK-EFM.
[BibTeX]
[DOI]
Xiangning Fan
,
Pengpeng Shi
,
Yilong Liao
,
Jian Tao
Proceedings of the Wired/Wireless Internet Communications, 2017


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