Yinhe Han

According to our database1, Yinhe Han authored at least 118 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2019
moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units.
IEEE Trans. Parallel Distrib. Syst., 2019

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs.
IEEE Trans. on Circuits and Systems, 2019

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator.
Computer Architecture Letters, 2019

System-level hardware failure prediction using deep learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving.
IEEE Robotics and Automation Letters, 2018

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency.
J. Comput. Sci. Technol., 2018

DimRouter: A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks.
J. Comput. Sci. Technol., 2018

See and Think: Disentangling Semantic Scene Completion.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

A retrospective evaluation of energy-efficient object detection solutions on embedded devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment.
Proceedings of the 55th Annual Design Automation Conference, 2018

PIMCH: Cooperative memory prefetching in processing-in-memory architecture.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.
IEEE Trans. VLSI Syst., 2017

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors.
IEEE Trans. Multi-Scale Computing Systems, 2017

Exploiting the Potential of Computation Reuse Through Approximate Computing.
IEEE Trans. Multi-Scale Computing Systems, 2017

Retention-Aware DRAM Assembly and Repair for Future FGR Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Dadu: Accelerating Inverse Kinematics for High-DOF Robots.
Proceedings of the 54th Annual Design Automation Conference, 2017

CNN-based object detection solutions for embedded heterogeneous multicore SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.
IEEE Trans. VLSI Syst., 2016

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.
IEEE Trans. VLSI Syst., 2016

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.
IEEE Trans. VLSI Syst., 2016

EcoUp: Towards Economical Datacenter Upgrading.
IEEE Trans. Parallel Distrib. Syst., 2016

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands.
ACM Trans. Design Autom. Electr. Syst., 2016

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores.
IEEE Trans. Computers, 2016

Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations.
Microelectronics Journal, 2016

Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing.
J. Comput. Sci. Technol., 2016

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.
Proceedings of the 53rd Annual Design Automation Conference, 2016

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.
Proceedings of the 53rd Annual Design Automation Conference, 2016

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.
Proceedings of the 53rd Annual Design Automation Conference, 2016

ACR: Enabling computation reuse for approximate computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Data Remapping for Static NUCA in Degradable Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.
IEEE Trans. VLSI Syst., 2015

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors.
IEEE Trans. VLSI Syst., 2015

A signal degradation reduction method for memristor ratioed logic (MRL) gates.
IEICE Electronic Express, 2015

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island.
Proceedings of the VLSI Design, Automation and Test, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.
IEEE Trans. VLSI Syst., 2014

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels.
IEEE Trans. VLSI Syst., 2014

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor.
ACM Trans. Design Autom. Electr. Syst., 2014

Reinventing Memory System Design for Many-Accelerator Architecture.
J. Comput. Sci. Technol., 2014

A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications.
J. Comput. Sci. Technol., 2014

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

SuperRange: Wide operational range power delivery design for both STV and NTV computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power DRAM refresh control scheme for 3D memory cube.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction.
IEEE Trans. VLSI Syst., 2013

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.
IEEE Trans. VLSI Syst., 2013

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router.
J. Comput. Sci. Technol., 2013

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.
J. Comput. Sci. Technol., 2013

On predicting NBTI-induced circuit aging by isolating leakage change.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

SmartCap: user experience-oriented power adaptation for smartphone's application processor.
Proceedings of the Design, Automation and Test in Europe, 2013

RISO: relaxed network-on-chip isolation for cloud processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
M-IVC: Applying multiple input vectors to co-optimize aging and leakage.
Microelectronics Journal, 2012

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation.
IEEE Trans. VLSI Syst., 2011

MicroFix: Using timing interpolation and delay sensors for power reduction.
ACM Trans. Design Autom. Electr. Syst., 2011

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.
IEEE Trans. Computers, 2011

Statistical lifetime reliability optimization considering joint effect of process variation and aging.
Integration, 2011

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.
IEICE Transactions, 2011

An abacus turn model for time/space-efficient reconfigurable routing.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Flex memory: Exploiting and managing abundant off-chip optical bandwidth.
Proceedings of the Design, Automation and Test in Europe, 2011

Eliminating data invalidation in debugging multiple-clock chips.
Proceedings of the Design, Automation and Test in Europe, 2011

Wear rate leveling: lifetime enhancement of PRAM with endurance variation.
Proceedings of the 48th Design Automation Conference, 2011

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A resilient on-chip router design through data path salvaging.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.
Journal of Systems Architecture - Embedded Systems Design, 2010

A Novel Post-Silicon Debug Mechanism Based on Suspect Window.
IEICE Transactions, 2010

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.
Proceedings of the 2011 IEEE International Test Conference, 2010

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.
Proceedings of the Design, Automation and Test in Europe, 2010

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.
IEEE Trans. VLSI Syst., 2009

A New Post-Silicon Debug Approach Based on Suspect Window.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A unified online Fault Detection scheme via checking of Stability Violation.
Proceedings of the Design, Automation and Test in Europe, 2009

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission.
IEICE Transactions, 2008

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. VLSI Syst., 2007

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.
J. Comput. Sci. Technol., 2007

2006
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.
IEEE Trans. Instrumentation and Measurement, 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions, 2006

Response compaction for system-on-a-chip based on advanced convolutional codes.
Science in China Series F: Information Sciences, 2006

An on-chip combinational decompressor for reducing test data volume.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fast Packet Classification using Group Bit Vector.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions, 2005

Using MUXs Network to Hide Bunches of Scan Chains.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Validation analysis and test flow optimization of VLSI chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Deterministic and low power BIST based on scan slice overlapping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

Pair Balance-Based Test Scheduling for SOCs.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Rapid and Energy-Efficient Testing for Embedded Cores.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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