Yu Gong

Orcid: 0000-0001-5465-9044

According to our database1, Yu Gong authored at least 18 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Co-Exploring Structured Sparsification and Low-Rank Tensor Decomposition for Compact DNNs.
IEEE Trans. Neural Networks Learn. Syst., April, 2025

TopV: Compatible Token Pruning with Inference Time Optimization for Fast and Low-Memory Multimodal Vision Language Model.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2025

2024
MoE-I<sup>2</sup>: Compressing Mixture of Experts Models through Inter-Expert Pruning and Intra-Expert Low-Rank Decomposition.
CoRR, 2024

ELRT: Efficient Low-Rank Training for Compact Convolutional Neural Networks.
CoRR, 2024

MOPED: Efficient Motion Planning Engine with Flexible Dimension Support.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

MoE-I²: Compressing Mixture of Experts Models through Inter-Expert Pruning and Intra-Expert Low-Rank Decomposition.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2024, 2024

DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Invited: Algorithm and Hardware Co-Design for Energy-Efficient Neural SLAM.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
ETTE: Efficient Tensor-Train-based Computing Engine for Deep Neural Networks.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

COMCAT: Towards Efficient Compression and Customization of Attention-Based Vision Models.
Proceedings of the International Conference on Machine Learning, 2023

Accelerable Lottery Tickets with the Mixed-Precision Quantization.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

HALOC: Hardware-Aware Automatic Low-Rank Compression for Compact Neural Networks.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition With Hierarchical Tucker Tensor Decomposition.
IEEE Trans. Computers, 2022

Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition with Hierarchical Tucker Tensor Decomposition.
CoRR, 2022

Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

HODEC: Towards Efficient High-Order DEcomposed Convolutional Neural Networks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

VLSI Hardware Architecture of Neural A* Path Planner.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022


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