Lingyi Huang

Orcid: 0000-0002-8204-4837

According to our database1, Lingyi Huang authored at least 16 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
MOPED: Efficient Motion Planning Engine with Flexible Dimension Support.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Lightweight design and realisation of autonomously balancing bicycles based on additive manufacturing technology.
Int. J. Comput. Appl. Technol., 2023

In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent Radar.
CoRR, 2023

ETTE: Efficient Tensor-Train-based Computing Engine for Deep Neural Networks.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

DynGMP: Graph Neural Network-Based Motion Planning in Unpredictable Dynamic Environments.
IROS, 2023

Invited Paper: In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent Radar.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition With Hierarchical Tucker Tensor Decomposition.
IEEE Trans. Computers, 2022

A novel fingerprint recognition method based on a Siamese neural network.
J. Intell. Syst., 2022

Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition with Hierarchical Tucker Tensor Decomposition.
CoRR, 2022

Robot Motion Planning as Video Prediction: A Spatio-Temporal Neural Network-based Motion Planner.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

VLSI Hardware Architecture of Neural A* Path Planner.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

2021
Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

VLSI Hardware Architecture of Stochastic Low-rank Tensor Decomposition.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2008
A High Speed CMOS Transmitter and Rail-to-Rail Receiver.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008


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