Yunyou Pu

Orcid: 0000-0002-0066-8890

According to our database1, Yunyou Pu authored at least 7 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Frequency-Agile Self-Interference Cancellation in a Wideband Compact Full-Duplex Receiver Using Cascaded Low-Noise and High-Delay-Bandwidth-Product APFs.
IEEE J. Solid State Circuits, June, 2026

A 196-MHz Bandwidth Transimpedance Amplifier with High Out-of-Band Rejection Employing Transmission Zeros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
A Wideband Frequency-Independent IQ Calibration Scheme With 3-GHz-UGB Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2025

A Compact Full-Duplex Receiver with Wideband Multi-Domain Hilbert-Transform-Equalization Cancellation Based on Multi-Stage APFs Achieving 65dB SIC Across 120MHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024

A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers.
IEEE J. Solid State Circuits, June, 2024

2023
A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023


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