We stand with Ukraine

We stand with Ukraine

Yuri Stepchenkov

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2022

Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems.

[BibT_eX]

[DOI]

,

Y. A. Stepchenkov

,

Yuri Rogdestvenski

,

Y. G. Diachenko

Autom. Remote. Control., 2022

2021

Design Validation of Recurrent Signal Processor FPGA prototype.

[BibT_eX]

[DOI]

Yury Stepchenkov

,

,

,

Proceedings of the IEEE East-West Design & Test Symposium, 2021

Self-Timed Storage Register Soft Error Tolerance Improvement.

[BibT_eX]

[DOI]

Yury Stepchenkov

,

,

Yury Rogdestvenski

,

,

Denis Diachenko

Proceedings of the IEEE East-West Design & Test Symposium, 2021

2020

Increasing Self-Timed Circuit Soft Error Tolerance.

[BibT_eX]

[DOI]

,

Yuri Stepchenkov

,

,

Yuri Rogdestvenski

,

Denis Diachenko

Proceedings of the IEEE East-West Design & Test Symposium, 2020

Improvement of the Quasi Delay-Insensitive Pipeline Noise Immunity.

[BibT_eX]

[DOI]

Yuri Stepchenkov

,

Yuri Rogdestvenski

,

Anton N. Kamenskih

,

,

Denis Diachenko

Proceedings of the 11th IEEE International Conference on Dependable Systems, 2020

2019

Advanced Indication of the Self-Timed Circuits.

[BibT_eX]

[DOI]

Yuri Stepchenkov

,

,

Yuri Rogdestvenski

,

,

Denis Diachenko

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Modeling and debugging tools development for recurrent architecture.

[BibT_eX]

[DOI]

,

Yury Stepchenkov

,

,

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Fault-Tolerance of Self-Timed Circuits.

[BibT_eX]

[DOI]

Yuri Stepchenkov

,

Anton N. Kamenskih

,

,

Yuri Rogdestvenski

,

Denis Y. Diachenko

Proceedings of the 10th International Conference on Dependable Systems, 2019

2016

Testing of software and hardware simulations of dataflow recurrent digital signal processor.

[BibT_eX]

[DOI]

Yuri Stepchenkov

,

,

,

,

Dimitry Shikunov

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Speed-independent fused multiply add and subtract unit.

[BibT_eX]

[DOI]

Yuri Stepchenkov

,

Victor N. Zakharov

,

Yuri Rogdestvenski

,

,

Nickolaj Morozov

,

Dmitri Stepchenkov

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015

Speed-independent floating point coprocessor.

[BibT_eX]

[DOI]

Y. A. Stepchenkov

,

Victor N. Zakharov

,

Y. V. Rogdestvenski

,

Y. G. Diachenko

,

,

D. Y. Stepchenkov

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Cell library for speed-independent VLSI.

[BibT_eX]

[DOI]

Y. A. Stepchenkov

,

Victor N. Zakharov

,

Y. G. Diachenko

,

,

D. Y. Stepchenkov

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Functional approach in self-timed circuit design.

[BibT_eX]

[DOI]

L. P. Plekhanov

,

Victor N. Zakharov

,

Y. A. Stepchenkov

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2009

Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation.

[BibT_eX]

[DOI]

Yuri Stepchenkov

,

,

Victor N. Zakharov

,

Yuri Rogdestvenski

,

Nikolai Morozov

,

Dmitri Stepchenkov

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Loading...