Zbigniew Jaworski

Orcid: 0000-0001-7935-6429

According to our database1, Zbigniew Jaworski authored at least 10 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2019
Highly Linear 4-bit Flash ADC Implemented in 22 nm FD-SOI Process.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2018
High Resolution Latched Comparator Implemented in 22 nm FD-SOI Process.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2017
A highly linear 4-bit DAC with 1 GHz sampling rate implemented in 28 nm FD-SOI process.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

2016
Verilog HDL model based thermometer-to-binary encoder with bubble error correction.
Proceedings of the 2016 MIXDES, 2016

2015
Optimization of capacitive divider for 8-bit DAC realized in 65 nm CMOS process.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Choosing the optimal HDL model of thermometer-to-binary encoder.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014
Fuzzy logic-based diagnostic algorithm for implantable cardioverter defibrillators.
Artif. Intell. Medicine, 2014

2004
Fuzzy logic controller for rate-adaptive heart pacemaker.
Appl. Soft Comput., 2004

1997
Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996
Architecture of a testable analog fuzzy logic controller.
IEEE Trans. Fuzzy Syst., 1996


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