Zhijingcheng Yu

Orcid: 0000-0001-6013-157X

According to our database1, Zhijingcheng Yu authored at least 7 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
Securing Mixed Rust with Hardware Capabilities.
CoRR, July, 2025

Anvil: A General-Purpose Timing-Safe Hardware Description Language.
CoRR, March, 2025

Caplification: Bridging Capability-Aware and Capability-Oblivious Software.
Proceedings of the 30th ACM Symposium on Access Control Models and Technologies, 2025

2023
Capstone: A Capability-based Foundation for Trustless Secure Memory Access (Extended Version).
CoRR, 2023

Capstone: A Capability-based Foundation for Trustless Secure Memory Access.
Proceedings of the 32nd USENIX Security Symposium, 2023

2022
Elasticlave: An Efficient Memory Model for Enclaves.
Proceedings of the 31st USENIX Security Symposium, 2022

2021
SmashEx: Smashing SGX Enclaves Using Exceptions.
Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021


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