Trevor E. Carlson

Orcid: 0000-0001-8742-134X

Affiliations:
  • National University of Singapore, Department of Computer Science


According to our database1, Trevor E. Carlson authored at least 77 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation.
IEEE Access, 2024

PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

GADGETSPINNER: A New Transient Execution Primitive Using the Loop Stream Detector.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Multiply-and-Fire: An Event-Driven Sparse Neural Network Accelerator.
ACM Trans. Archit. Code Optim., December, 2023

Pac-Sim: Simulation of Multi-threaded Workloads using Intelligent, Live Sampling.
CoRR, 2023

Mitigating Speculation-based Attacks through Configurable Hardware/Software Co-design.
CoRR, 2023

New Cross-Core Cache-Agnostic and Prefetcher-based Side-Channels and Covert-Channels.
CoRR, 2023

Capstone: A Capability-based Foundation for Trustless Secure Memory Access (Extended Version).
CoRR, 2023

3DRA: Dynamic Data-Driven Reconfigurable Architecture.
IEEE Access, 2023

Capstone: A Capability-based Foundation for Trustless Secure Memory Access.
Proceedings of the 32nd USENIX Security Symposium, 2023

Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

HidFix: Efficient Mitigation of Cache-Based Spectre Attacks Through Hidden Rollbacks.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Efficient Instruction Scheduling Using Real-time Load Delay Tracking.
ACM Trans. Comput. Syst., 2022

Rectified Linear Postsynaptic Potential Function for Backpropagation in Deep Spiking Neural Networks.
IEEE Trans. Neural Networks Learn. Syst., 2022

Multiply-and-Fire (MNF): An Event-driven Sparse Neural Network Accelerator.
CoRR, 2022

A Cross-Prefetcher Schedule Optimization Methodology.
IEEE Access, 2022

Elasticlave: An Efficient Memory Model for Enclaves.
Proceedings of the 31st USENIX Security Symposium, 2022

Fast, Robust and Accurate Detection of Cache-Based Spectre Attack Phases.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Leaking Control Flow Information via the Hardware Prefetcher.
CoRR, 2021

Mitigating Power Attacks through Fine-Grained Instruction Reordering.
CoRR, 2021

Sentry-NoC: a statically-scheduled NoC for secure SoCs.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

ELFies: Executable Region Checkpoints for Performance Analysis and Simulation.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

NOREBA: a compiler-informed non-speculative out-of-order commit processor.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Agile and Open-Source Hardware.
IEEE Micro, 2020

CARGO : Context Augmented Critical Region Offload for Network-bound datacenter Workloads.
CoRR, 2020

SOTERIA: In Search of Efficient Neural Networks for Private Inference.
CoRR, 2020

You Only Spike Once: Improving Energy-Efficient Neuromorphic Inference to ANN-Level Accuracy.
CoRR, 2020

PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures.
IEEE Comput. Archit. Lett., 2020

A Framework for Developing Critical Literacies in Computer Architecture Education.
Proceedings of the IEEE International Conference on Teaching, 2020

Secure Your SoC: Building System-an-Chip Designs for Security.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Laser Attack Benchmark Suite.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit.
J. Signal Process. Syst., 2019

Sampled Simulation of Task-Based Programs.
IEEE Trans. Computers, 2019

Directed Statistical Warming through Time Traveling.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
Static Instruction Scheduling for High Performance on Limited Hardware.
IEEE Trans. Computers, 2018

Non-Speculative Load Reordering in Total Store Ordering.
IEEE Micro, 2018

Power-performance tradeoffs in data center servers: DVFS, CPU pinning, horizontal, and vertical scaling.
Future Gener. Comput. Syst., 2018

Active Learning to Develop Key Research Skills in Master's Level Computer Science Coursework.
Proceedings of the IEEE International Conference on Teaching, 2018

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-Based GPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2017
Transcending Hardware Limits with Software Out-of-Order Processing.
IEEE Comput. Archit. Lett., 2017

A taxonomy of out-of-order instruction commit.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Non-Speculative Load-Load Reordering in TSO.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

A graphics tracing framework for exploring CPU+GPU memory systems.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Analyzing graphics workloads on tile-based GPUs.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Clairvoyance: look-ahead compile-time scheduling.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

Exploring the Performance Limits of Out-of-order Commit.
Proceedings of the Computing Frontiers Conference, 2017

POSTER: Putting the G back into GPU/CPU Systems Research.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics.
IEEE Trans. Computers, 2016

CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profiling.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

CoolSim: Eliminating traditional cache warming with fast, virtualized profiling.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015
Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization.
IEEE Comput. Archit. Lett., 2015

Long term parking (LTP): criticality-aware resource allocation in OOO processors.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Micro-architecture independent analytical processor performance and power modeling.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

The load slice core microarchitecture.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Chrysso: an integrated power manager for constrained many-core processors.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
An Evaluation of High-Level Mechanistic Core Models.
ACM Trans. Archit. Code Optim., 2014

BarrierPoint: Sampled simulation of multi-threaded applications.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor.
Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, 2014

Undersubscribed threading on clustered cache architectures.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling.
ACM Trans. Archit. Code Optim., 2013

Node Performance and Energy Analysis with the Sniper Multi-core Simulator.
Proceedings of the Tools for High Performance Computing 2013, 2013

Sampled simulation of multi-threaded applications.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012
Power-aware multi-core simulation for early design stage hardware/software co-optimization.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation.
Proceedings of the Conference on High Performance Computing Networking, 2011

Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

2009
Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.
IEEE Trans. Signal Process., 2009

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009


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