Zhipeng Cao

Orcid: 0000-0002-2804-9741

Affiliations:

Information Engineering University, National Digital Switching System Engineering and Technological Research Center, China
People's Liberation Army Strategic Support Force, Institute of Information Technology

According to our database¹, Zhipeng Cao authored at least 8 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2025

Architectural Exploration for Waferscale Switching System.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

MAHR: A Multi-Application Hybrid Reconfigurable Mechanism for Energy-Efficient Chiplet Interconnection Network.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., January, 2025

A Multi-Objective Task Mapping Method for Enhancing Security Against Hardware Trojans in Heterogeneous Multi-Core System.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2025

Enhancing interconnection network topology for chiplet-based systems: An automated design framework.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2025

2024

ETRS: efficient turn restrictions setting method for boundary routers in chiplet-based systems.

[BibT_eX]

[DOI]

J. Supercomput., September, 2024

LBDR: A load-balanced deadlock-free routing strategy for chiplet systems.

[BibT_eX]

[DOI]

Integr., 2024

Modeling and Analysis of Waferscale Switching Network with Multiple System Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2021

Enhanced System Design and Scheduling Strategy for Switches in Time-Sensitive Networking.

[BibT_eX]

[DOI]

IEEE Access, 2021

Zhipeng Cao

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