Zhiyuan Zhang

Orcid: 0009-0000-2669-5654

Affiliations:
  • University of Melbourne, VIC, Australia
  • University of Adelaide, SA, Australia (former)


According to our database1, Zhiyuan Zhang authored at least 12 papers between 2022 and 2025.

Collaborative distances:

Timeline

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Bibliography

2025
Transparent Decompilation for Timing Side-Channel Analyses.
CoRR, January, 2025



Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants).
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024
The Security Impact of Microarchitecture Optimizations.
PhD thesis, 2024

TeeJam: Sub-Cache-Line Leakages Strike Back.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Evict+Spec+Time: Exploiting Out-of-Order Execution to Improve Cache-Timing Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Protecting cryptographic code against Spectre-RSB.
IACR Cryptol. ePrint Arch., 2024

2023
BunnyHop: Exploiting the Instruction Prefetcher.
Proceedings of the 32nd USENIX Security Symposium, 2023

Ultimate SLH: Taking Speculative Load Hardening to the Next Level.
Proceedings of the 32nd USENIX Security Symposium, 2023

2022
Breaking and Fixing Speculative Load Hardening.
IACR Cryptol. ePrint Arch., 2022

Side-Channeling the Kalyna Key Expansion.
Proceedings of the Topics in Cryptology - CT-RSA 2022, 2022


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