Yuval Yarom

According to our database1, Yuval Yarom authored at least 45 papers between 2008 and 2020.

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Bibliography

2020
Cache vs. Key-Dependency: Side Channeling an Implementation of Pilsung.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

LadderLeak: Breaking ECDSA With Less Than One Bit Of Nonce Leakage.
IACR Cryptol. ePrint Arch., 2020

CacheOut: Leaking Data on Intel CPUs via Cache Evictions.
CoRR, 2020

Meltdown: reading kernel memory from user space.
Commun. ACM, 2020

Enterprise Security Architecture: Mythology or Methodology?
Proceedings of the 22nd International Conference on Enterprise Information Systems, 2020

2019
Breaking Virtual Memory Protection and the SGX Ecosystem with Foreshadow.
IEEE Micro, 2019

Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers.
IACR Cryptol. ePrint Arch., 2019

Pseudorandom Black Swans: Cache Attacks on CTR_DRBG.
IACR Cryptol. ePrint Arch., 2019

Fallout: Reading Kernel Writes From User Space.
CoRR, 2019

Robust Website Fingerprinting Through the Cache Occupancy Channel.
Proceedings of the 28th USENIX Security Symposium, 2019

Spectre Attacks: Exploiting Speculative Execution.
Proceedings of the 2019 IEEE Symposium on Security and Privacy, 2019

Time Protection: The Missing OS Abstraction.
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

Fallout: Leaking Data on Meltdown-resistant CPUs.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

2018
Spectre Attacks: Exploiting Speculative Execution.
meltdownattack.com, 2018

Meltdown
meltdownattack.com, 2018

CacheQuote: Efficiently Recovering Long-term Secrets of SGX EPID via Cache Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware.
J. Cryptographic Engineering, 2018

The 9 Lives of Bleichenbacher's CAT: New Cache ATtacks on TLS Implementations.
IACR Cryptol. ePrint Arch., 2018

Drive-by Key-Extraction Cache Attacks from Portable Code.
IACR Cryptol. ePrint Arch., 2018

Meltdown: Reading Kernel Memory from User Space.
Proceedings of the 27th USENIX Security Symposium, 2018

Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution.
Proceedings of the 27th USENIX Security Symposium, 2018

Another Flip in the Wall of Rowhammer Defenses.
Proceedings of the 2018 IEEE Symposium on Security and Privacy, 2018

The Effect of Common Vulnerability Scoring System Metrics on Vulnerability Exploit Delay.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

No Security Without Time Protection: We Need a New Hardware-Software Contract.
Proceedings of the 9th Asia-Pacific Workshop on Systems, 2018

2017
CacheBleed: a timing attack on OpenSSL constant-time RSA.
J. Cryptographic Engineering, 2017

To BLISS-B or not to be - Attacking strongSwan's Implementation of Post-Quantum Signatures.
IACR Cryptol. ePrint Arch., 2017

Modifying an Enciphering Scheme after Deployment.
IACR Cryptol. ePrint Arch., 2017

May the Fourth Be With You: A Microarchitectural Side Channel Attack on Several Real-World Applications of Curve25519.
IACR Cryptol. ePrint Arch., 2017

Sliding right into disaster: Left-to-right sliding windows leak.
IACR Cryptol. ePrint Arch., 2017

USB Snooping Made Easy: Crosstalk Leakage Attacks on USB Hubs.
Proceedings of the 26th USENIX Security Symposium, 2017

2016
ECDSA Key Extraction from Mobile Devices via Nonintrusive Physical Side Channels.
IACR Cryptol. ePrint Arch., 2016

"Make Sure DSA Signing Exponentiations Really are Constant-Time".
IACR Cryptol. ePrint Arch., 2016

Flush, Gauss, and Reload - A Cache Attack on the BLISS Lattice-Based Signature Scheme.
IACR Cryptol. ePrint Arch., 2016

Do Hardware Cache Flushing Operations Actually Meet Our Expectations?
CoRR, 2016

CATalyst: Defeating last-level cache side channel attacks in cloud computing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Evaluation and Cryptanalysis of the Pandaka Lightweight Cipher.
IACR Cryptol. ePrint Arch., 2015

Mapping the Intel Last-Level Cache.
IACR Cryptol. ePrint Arch., 2015

Exploiting Transformations of the Galois Configuration to Improve Guess-and-Determine Attacks on NFSRs.
IACR Cryptol. ePrint Arch., 2015

Amplifying Side Channels Through Performance Degradation.
IACR Cryptol. ePrint Arch., 2015

Last-Level Cache Side-Channel Attacks are Practical.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

2014
Recovering OpenSSL ECDSA Nonces Using the FLUSH+RELOAD Cache Side-channel Attack.
IACR Cryptol. ePrint Arch., 2014

Just a Little Bit More.
IACR Cryptol. ePrint Arch., 2014

"Ooh Aah... Just a Little Bit" : A small amount of side channel can go a long way.
IACR Cryptol. ePrint Arch., 2014

2013
Flush+Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack.
IACR Cryptol. ePrint Arch., 2013

2008
Estimating camera overlap in large and growing networks.
Proceedings of the 2008 Second ACM/IEEE International Conference on Distributed Smart Cameras, 2008


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