Zih-Heng Chen

Affiliations:

I-Shou University, Kaohsiung, Taiwan

According to our database¹, Zih-Heng Chen authored at least 10 papers between 2006 and 2011.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2011

A fast parallel (23, 12, 7) QR decoder based on syndrome-weight determination.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2011

2010

A Result on Zetterberg Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2010

2008

Design of simple and high speed VLSI core for the protection of mass storages.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A new decoder for binary quadratic residue code with irreducible generator polynomial.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Reconfigurable system for high-speed and diversified AES using FPGA.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2007

The Secure DAES Design for Embedded System Application.

[BibT_eX]

[DOI]

Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2007

2006

New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The Inverse Matrix for the Conversion Between Standard and Normal Bases.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Low Complexity Architecture for Multiplicative Inversion in GF(2m).

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Another Look at the Sequential Multiplier over Normal Bases.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Zih-Heng Chen

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