A. David Selvakumar

According to our database, A. David Selvakumar authored at least 18 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.

Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2021

PositGen-A Verification Suite for Posit Arithmetic.

Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor.

Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Formal Verification and Analysis of a Pseudo Random Number Generator.

David Selvakumar, J. Mervin, Shashikala Gunderao Pattanshetty, Vivian Desalphine

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment.

Venkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, David Selvakumar, Sankha Saha

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus.

Venkata Reddy Kolagatla, Vivian Desalphine, David Selvakumar

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020

A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture.

Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA.

Vivian Desalphine, Somya Dashora, Laxita Mali, Suhas K, Aneesh Raveendran, David Selvakumar

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures.

Shabbir Darbar, J. Mervin, David Selvakumar

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU.

Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor.

Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. David Selvakumar

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2015

RISC-V out-of-order data conversion co-processor.

Aneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Out of order floating point coprocessor for RISC V ISA.

Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, Vivian Desalphine

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Wireless sensor device hardware architecture - Design and analysis for high availability.

David Selvakumar, Kaushik Nanda, Hari Babu Pasupuleti

Proceedings of the 7th International Conference on New Technologies, Mobility and Security, 2015

2011

Wireless sensor node variants and their application domains.

Ramana Rao, Haribabu, David Selvakumar

Proceedings of the 1st International Conference on Wireless Technologies for Humanitarian Relief, 2011

2006

Bitslice Implementation of AES.

Chester Rebeiro, A. David Selvakumar, A. S. L. Devi

Proceedings of the Cryptology and Network Security, 5th International Conference, 2006

2005

SCADA with Fault Tolerant CORBA on Fault Tolerant LANE ATM.

A. David Selvakumar, Chester Rebeiro, R. Pitchiah

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Design, Implementation and Performance of Fault-Tolerant Message Passing Interface (MPI).

A. David Selvakumar, P. M. Sobha, G. C. Ravindra, R. Pitchiah

Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004