Abhaya Asthana

According to our database1, Abhaya Asthana authored at least 32 papers between 1978 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


MAYOR: Machine Learning and Analytics for Automated Operations and Recovery.
Proceedings of the 28th International Conference on Computer Communication and Networks, 2019

DARN: Dynamic Baselines for Real-time Network Monitoring.
Proceedings of the 4th IEEE Conference on Network Softwarization and Workshops, 2018

Recent Advances in Software Reliability Assurance.
Proceedings of the 2018 IEEE International Symposium on Software Reliability Engineering Workshops, 2018

BRACE: Cloud-Based Software Reliability Assurance.
Proceedings of the 2017 IEEE International Symposium on Software Reliability Engineering Workshops, 2017

Integrative Software Design for Reliability: Beyond Models and Defect Prediction.
Bell Labs Technical Journal, 2012

End-to-end service availability support: Theory and application.
Bell Labs Technical Journal, 2010

Multimedia Servers.
Proceedings of the Encyclopedia of Multimedia, 2006

Multimedia in Education.
Proceedings of the Encyclopedia of Multimedia, 2006

Analyzing network availability of a mobile data network: A case study.
Bell Labs Technical Journal, 2006

End-to-end availability considerations for services over IMS.
Bell Labs Technical Journal, 2006

Hybrid network management.
Bell Labs Technical Journal, 2000

A Parallel Architecture for Network Control and Mobility Tracking in Wireless Systems.
Wireless Personal Communications, 1997

Logic-enhanced memory for high performance databases.
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1997

Kaleido: An Environment for Composing Networked Multimedia Applications.
Proceedings of the 6th International Symposium on High Performance Distributed Computing, 1997

An Experimental Active-Memory-Based I/O Subsystem.
Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996

Run-Time Parallelization of Sequential Database Programs.
Proceedings of the CIKM '95, Proceedings of the 1995 International Conference on Information and Knowledge Management, November 28, 1995

An experimental active memory based I/O subsystem.
SIGARCH Computer Architecture News, 1994

An Indoor Wireless System for Personalized Shopping Assistance.
Proceedings of the First Workshop on Mobile Computing Systems and Applications, 1994

SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A Memory Participative Architecture for High Performance Communication Systems.
Proceedings of the Proceedings IEEE INFOCOM '94, 1994

Towards a Programming Environment for a Computer with Intelligent Memory.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

SWIM Active Memory: Architecture and Applications.
Proceedings of the Technology and Foundations - Information Processing '94, Volume 1, Proceedings of the IFIP 13th World Computer Congress, Hamburg, Germany, 28 August, 1994

An Experimental Active-Memory-Based Network Environment.
Proceedings of the Third International Symposium on High Performance Distributed Computing, 1994

Towards a Gigabit IP Router.
J. High Speed Networks, 1992

The Design of a Back-end Object Management System.
Proceedings of the Code Generation, 1991

An Intelligent Memory Transaction Engine.
Proceedings of the Database Machines, Sixth International Workshop, 1989

The Architecture of Massively Parallel Numeric Processor.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer.
Proceedings of the International Conference on Parallel Processing, 1989

The trap as a control flow mechanism.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

A VLSI Building Block for Massively Parallel Computation.
Proceedings of the International Conference on Fifth Generation Computer Systems, 1988

A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling.
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, 1982

Design and Control of a Three-Stage Switch Matrix in the Presence of Fan-Out.
IEEE Trans. Computers, 1978