Aditya Jagirdar

According to our database1, Aditya Jagirdar authored at least 3 papers between 2007 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
Vendor-agnostic native compression engine.
Proceedings of the 2011 IEEE International Test Conference, 2010

2008
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
A TMR Scheme for SEU Mitigation in Scan Flip-Flops.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007


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