Jeff Rearick

According to our database, Jeff Rearick authored at least 45 papers between 1993 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Refreshing the JTAG Family.

Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Welcome Message ITC 2023.

Li-C. Wang, Jeff Rearick

Proceedings of the IEEE International Test Conference, 2023

2022

IEEE P1687.1: Extending the Network Boundaries for Test.

Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo

Proceedings of the IEEE International Test Conference, 2022

2021

Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces.

Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices.

Hans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne

Proceedings of the IEEE International Test Conference, 2020

Modeling Novel Non-JTAG IEEE 1687-Like Architectures.

Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick

Proceedings of the IEEE International Test Conference, 2020

Linking Chip, Board, and System Test via Standards.

Michele Portolan, Jeff Rearick, Martin Keim

Proceedings of the IEEE European Test Symposium, 2020

2019

Innovative Practices on IEEE 1687.xyz.

Jeff Rearick, Alfred L. Crouch, Hans Martin von Staudt

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Innovative practices on quality levels of A/MS devices.

Wim Dobbelaere, On Semi, Massimo Violante, Turin Polytechnic, Jeff Rearick

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017

Unleashing Fury: A New Paradigm for 3-D Design and Test.

Michael Alfano, Bryan Black, Jeff Rearick, Joseph Siegel, Michael Su, Julius Din

IEEE Des. Test, 2017

Use models for extending IEEE 1687 to analog test.

Peter Sarson, Jeff Rearick

Proceedings of the IEEE International Test Conference, 2017

Maximizing scan pin and bandwidth utilization with a scan routing fabric.

Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood

Proceedings of the IEEE International Test Conference, 2017

2016

Streaming Access to ADCs and DACs for Mixed-Signal ATPG.

Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick

IEEE Des. Test, 2016

Toward more efficient scan data bandwidth utilization on modern SOCs.

Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015

Streaming fast access to ADCs and DACs for mixed-signal ATPG.

Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns.

Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick

Proceedings of the 2014 International Test Conference, 2014

2013

Magical thinking applied to test engineering reality (and vice versa).

Jeff Rearick

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

Re-using chip level DFT at board level.

Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Structural tests of slave clock gating in low-power flip-flop.

Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010

Selecting the most relevant structural Fmax for system Fmax correlation.

Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Vendor-agnostic native compression engine.

Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing.

Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick

IEEE Des. Test Comput., 2009

IEEE P1687 IJTAG a presentation of current technology.

Ken Posse, Al Crouch, Jeff Rearick

Proceedings of the 2009 IEEE International Test Conference, 2009

Cache-resident self-testing for I/O circuitry.

Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Overview of Debug Standardization Activities.

Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick

IEEE Des. Test Comput., 2008

This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company.

Jeff Rearick

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.

Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick

IEEE Des. Test Comput., 2007

Test cost reduction for the AMD™ Athlon processor using test partitioning.

Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick

Proceedings of the 2007 IEEE International Test Conference, 2007

Embedded Test Features for High-Speed Serial I/O.

Jeff Rearick

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing.

Jeff Rearick, Aaron Volz

Proceedings of the 2006 IEEE International Test Conference, 2006

A Survey of Test Problems and Solutions.

Jeff Rearick

Proceedings of the 2006 IEEE International Test Conference, 2006

IEEE P1687: Toward Standardized Access of Embedded Instrumentation.

Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Calibrating clock stretch during AC scan testing.

Jeff Rearick, Richard Rodgers

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

IJTAG (internal JTAG): a step toward a DFT standard.

Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Integrating Boundary Scan into Multi-GHz I/O Circuitry.

Jeff Rearick, Sylvia Patterson, Krista Dorner

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture.

Manish Sharma, Janak H. Patel, Jeff Rearick

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

First IC Validation of IEEE Std. 1149.6.

Suzette Vandivier, Mark Wahl, Jeff Rearick

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2001

Too much delay fault coverage is a bad thing.

Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Frequency detection-based boundary-scan testing of AC coupled nets.

Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Deception by design: fooling ourselves with gate-level models.

Peter C. Maxwell, Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Practical scan test generation and application for embedded FIFOs.

Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Buying time for the stuck-at fault model.

Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Estimation of defect-free IDDQ in submicron circuits using switch level simulation.

Peter C. Maxwell, Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

The Case of Partial Scan.

Jeff Rearick

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1993

Fast and Accurate CMOS Bridging Fault Simulation.

Jeff Rearick, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993