Adrian Tatulian
Orcid: 0000-0001-5632-6518
According to our database1,
Adrian Tatulian
authored at least 8 papers
between 2019 and 2025.
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Bibliography
2025
PeerCollate: A Peer-Centered Team Learning Approach to Digitized STEM Lab Activities and Assessments.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
2023
Scalable Reasoning and Sensing Using Processing-In-Memory With Hybrid Spin/CMOS-Based Analog/Digital Blocks.
IEEE Trans. Emerg. Top. Comput., 2023
Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Nonuniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Generalized Exponentiation Using STT Magnetic Tunnel Junctions: Circuit Design, Performance, and Application to Neural Network Gradient Decay.
SN Comput. Sci., 2022
2021
A Reconfigurable and Compact Spin-Based Analog Block for Generalizable n<sup>th</sup> Power and Root Computation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
2019
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019