Ronald F. DeMara
Orcid: 0000-0001-6864-7255Affiliations:
- University of Central Florida, Orlando, FL, USA
According to our database1,
Ronald F. DeMara
authored at least 177 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on zbmath.org
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on orcid.org
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on cal.ucf.edu
On csauthors.net:
Bibliography
2024
Promoting Community of Inquiry in Synchronous Team Design Activities for Remote Engineering Laboratory Instruction.
IEEE Trans. Educ., February, 2024
Guest Editorial IEEE Transactions on Emerging Topics in Special Section on Emerging In-Memory Computing Architectures and Applications.
IEEE Trans. Emerg. Top. Comput., 2024
2023
Algorithm and hardware co-design co-optimization framework for LSTM accelerator using quantized fully decomposed tensor train.
Internet Things, July, 2023
Energy-Efficient Recurrent Neural Network With MRAM-Based Probabilistic Activation Functions.
IEEE Trans. Emerg. Top. Comput., 2023
Scalable Reasoning and Sensing Using Processing-In-Memory With Hybrid Spin/CMOS-Based Analog/Digital Blocks.
IEEE Trans. Emerg. Top. Comput., 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Genetic Algorithm for Combinational Logic Circuit Synthesis Using Directed Graph Primitives.
Proceedings of the International Conference on Machine Learning and Applications, 2023
2022
Nonuniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Generalized Exponentiation Using STT Magnetic Tunnel Junctions: Circuit Design, Performance, and Application to Neural Network Gradient Decay.
SN Comput. Sci., 2022
Hardware Oriented Strip-wise Optimization (HOSO) Framework for Efficient Deep Neural Network.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Utilization of Data Augmentation Techniques to Enhance Learning with Sparse Datasets.
Proceedings of the 5th International Conference on Artificial Intelligence for Industries, 2022
2021
Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture.
IEEE Trans. Emerg. Top. Comput., 2021
Probabilistic Interpolation Recoder for Energy-Error-Product Efficient DBNs With p-Bit Devices.
IEEE Trans. Emerg. Top. Comput., 2021
Longitudinal Learning Outcomes from Engineering-Specific Adaptions of Hybrid Online Undergraduate Instruction.
Int. J. Emerg. Technol. Learn., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Reconfigurable and Compact Spin-Based Analog Block for Generalizable n<sup>th</sup> Power and Root Computation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Embedded STT-MRAM Energy Analysis for Intermittent Applications using Mean Standby Duration.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
IEEE Trans. Computers, 2020
Modular Simulation Framework for Process Variation Analysis of MRAM-based Deep Belief Networks.
CoRR, 2020
Electrically-Tunable Stochasticity for Spin-based Neuromorphic Circuits: Self-Adjusting to Variation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers.
IEEE Trans. Emerg. Top. Comput., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems.
IEEE Trans. Computers, 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture.
Integr., 2019
Leveraging design diversity to counteract process variation: theory, method, and FPGA toolchain to increase yield and resilience in-situ.
IET Comput. Digit. Tech., 2019
Implementing Student-Created Video in Engineering: An Active Learning Approach for Exam Preparedness.
Int. J. Eng. Pedagog., 2019
Engineering assessment strata: A layered approach to evaluation spanning Bloom's taxonomy of learning.
Educ. Inf. Technol., 2019
CoRR, 2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience.
CoRR, 2019
Computer, 2019
Efficacy and perceptions of assessment digitization within a large-enrollment mechanical and aerospace engineering course.
Comput. Appl. Eng. Educ., 2019
Energy Efficient Mobile Service Computing With Differential Spintronic-C-Elements: A Logic-in-Memory Asynchronous Computing Paradigm.
IEEE Access, 2019
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
An Ultra-Low Power Spintronic Stochastic Spiking Neuron with Self-Adaptive Discrete Sampling.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
IRC Cross-Layer Design Exploration of Intermittent Robust Computation Units for IoTs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Virtualized Active Learning for Undergraduate Engineering Disciplines (VALUED): A Pilot in a Large Enrollment STEM Classroom.
Proceedings of the IEEE Frontiers in Education Conference, 2019
Proceedings of the IEEE Frontiers in Education Conference, 2019
2018
Designing and Evaluating Redundancy-Based Soft-Error Masking on a Continuum of Energy versus Robustness.
IEEE Trans. Sustain. Comput., 2018
IEEE Trans. Emerg. Top. Comput., 2018
Elevating Learner Achievement Using Formative Electronic Lab Assessments in the Engineering Laboratory: A Viable Alternative to Weekly Lab Reports.
IEEE Trans. Educ., 2018
Survivability Modeling and Resource Planning for Self-Repairing Reconfigurable Device Fabrics.
IEEE Trans. Cybern., 2018
IEEE Trans. Computers, 2018
IEEE Trans. Computers, 2018
SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter leveraging SHE-enabled Domain Wall Motion devices.
Microelectron. J., 2018
Hybrid spin-CMOS stochastic spiking neuron for high-speed emulation of In vivo neuron dynamics.
IET Comput. Digit. Tech., 2018
Energy-Aware Adaptive Rate and Resolution Sampling of Spectrally Sparse Signals Leveraging VCMA-MTJ Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Non-Volatile Memory Trends: Toward Improving Density and Energy Profiles across the System Stack.
Computer, 2018
Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization.
IEEE Access, 2018
Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile Applications.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Lockdown Computerized Testing Interwoven with Rapid Remediation: A Crossover Study within a Mechanical Engineering Core Course.
Proceedings of the IEEE Frontiers in Education Conference, 2018
2017
Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures.
IEEE Trans. Emerg. Top. Comput., 2017
Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Computers, 2017
Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency.
ACM J. Emerg. Technol. Comput. Syst., 2017
Integr., 2017
Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing.
IET Circuits Devices Syst., 2017
R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices.
CoRR, 2017
AI in Informal Science Education: Bringing Turing Back to Life to Perform the Turing Test.
Int. J. Artif. Intell. Educ., 2017
Secure intermittent-robust computation for energy harvesting device security and outage resilience.
Proceedings of the 2017 IEEE SmartWorld, 2017
Variation-immune resistive Non-Volatile Memory using self-organized sub-bank circuit designs.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Process variation immune and energy aware sense amplifiers for resistive non-volatile memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Exploring the Effect of Compiler Optimizations on the Reliability of HPC Applications.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Heterogeneous Technology Configurable Fabrics for Field-Programmable Co-Design of CMOS and Spin-Based Devices.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
IEEE Trans. Computers, 2016
Fast Online Diagnosis and Recovery of Reconfigurable Logic Fabrics Using Design Disjunction.
IEEE Trans. Computers, 2016
Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Enhancement.
CoRR, 2016
Intrinsic Evolution of Truncated Puiseux Series on a Mixed-Signal Field-Programmable SoC.
IEEE Access, 2016
Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
Microelectron. J., 2015
ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism.
Microprocess. Microsystems, 2015
J. Circuits Syst. Comput., 2015
Power and quality-aware image processing soft-resilience using online multi-objective GAs.
Int. J. Comput. Vis. Robotics, 2015
Proceedings of the International Conference for High Performance Computing, 2015
Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics.
Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
Self-Scaling Evolution of analog computation circuits with digital accuracy refinement.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
J. Signal Process. Syst., 2014
Passing an Enhanced Turing Test - Interacting with Lifelike Computer Representations of Specific Individuals.
J. Intell. Syst., 2014
Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input.
Int. J. Reconfigurable Comput., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014
Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Computers, 2013
Microprocess. Microsystems, 2013
Passing an Enhanced Turing Test - Interacting with Lifelike Computer Representations of Specific Individuals.
J. Intell. Syst., 2013
An Extended Turing Test: A Context Based Approach Designed to Educate Youth in Computing.
Proceedings of the Modeling and Using Context, 2013
2012
Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms.
Appl. Soft Comput., 2012
Proceedings of the 2012 Spring Simulation Multiconference, 2012
2011
Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption.
Int. J. Reconfigurable Comput., 2011
ACM Comput. Surv., 2011
Appl. Soft Comput., 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
2010
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
2009
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration.
ACM Trans. Embed. Comput. Syst., 2009
A Sustainable Model for Integrating Current Topics in Machine Learning Research Into the Undergraduate Curriculum.
IEEE Trans. Educ., 2009
Proceedings of the IEEE International Conference on Systems, 2009
Proceedings of the International Conference on Information, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores.
Proceedings of the 2008 International Conference on Embedded Systems & Applications, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
Pipelining of Fuzzy ARTMAP without matchtracking: Correctness, performance bound, and Beowulf evaluation.
Neural Networks, 2007
Self-Timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion.
J. Circuits Syst. Comput., 2007
Int. J. Netw. Secur., 2007
Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices.
Proceedings of the FPL 2007, 2007
Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
2006
IEEE Trans. Syst. Man Cybern. Part B, 2006
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integr., 2006
Mitigation of Insider Risks using Distributed Agent Detection, Filtering, and Signaling.
Int. J. Netw. Secur., 2006
CONFIDANT: Collaborative Object Notification Framework for Insider Defense using Autonomous Network Transactions.
Auton. Agents Multi Agent Syst., 2006
A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
A combinatorial group testing method for FPGA fault location.
Proceedings of the IASTED International Conference on Advances in Computer Science and Technology, 2006
2005
Data-partitioning using the Hilbert space filling curves: Effect on the speed of convergence of Fuzzy ARTMAP for large database problems.
Neural Networks, 2005
Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005
Self-Checking Fault Detection using Discrepancy Mirrors.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005
Consensus-Based Evaluation for Fault Isolation and On-line Evolutionary Regeneration.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2005
A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005
Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005
2004
Simul. Model. Pract. Theory, 2004
Informing Sci. Int. J. an Emerg. Transdiscipl., 2004
Comput. Secur., 2004
A Partitioned Fuzzy ARTMAP Implementation for Fast Processing of Large Databases on Sequential Machines.
Proceedings of the Seventeenth International Florida Artificial Intelligence Research Society Conference, 2004
Feedback Techniques for Dual-Rail Self-Timed Circuits.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
Parallel Comput., 2003
CRCD in machine learning at the University of Central Florida preliminary experiences.
Proceedings of the 8th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2003
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003
2002
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.
J. Syst. Archit., 2002
Communication Pattern Based Methodology for Performance Analysis of Termination Detection Schemes.
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002
2001
A Connectionist-Symbolic Approach to Modeling Agent Behavior: Neural Networks Grouped by Contexts.
Proceedings of the Modeling and Using Context, 2001
2000
J. Circuits Syst. Comput., 2000
1994
Proceedings of the 8th International Symposium on Parallel Processing, 1994
1993
A Parallel Computational Model for Integrated Speech and Natural Language Understanding.
IEEE Trans. Computers, 1993
1991
Proceedings of the First International Conference on Parallel and Distributed Information Systems (PDIS 1991), 1991
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Performance Indices for Parallel Marker-Propagation.
Proceedings of the International Conference on Parallel Processing, 1991