Ronald F. DeMara

According to our database1, Ronald F. DeMara authored at least 139 papers between 1991 and 2019.

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2019
Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers.
IEEE Trans. Emerging Topics Comput., 2019

Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems.
IEEE Trans. Computers, 2019

Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons.
JETC, 2019

Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture.
Integration, 2019

Leveraging design diversity to counteract process variation: theory, method, and FPGA toolchain to increase yield and resilience in-situ.
IET Computers & Digital Techniques, 2019

Engineering assessment strata: A layered approach to evaluation spanning Bloom's taxonomy of learning.
EAIT, 2019

Leveraging Stochasticity for In Situ Learning in Binarized Deep Neural Networks.
IEEE Computer, 2019

Efficacy and perceptions of assessment digitization within a large-enrollment mechanical and aerospace engineering course.
Comp. Applic. in Engineering Education, 2019

Energy Efficient Mobile Service Computing With Differential Spintronic-C-Elements: A Logic-in-Memory Asynchronous Computing Paradigm.
IEEE Access, 2019

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Clockless Spin-based Look-Up Tables with Wide Read Margin.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

HSC-FPGA.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Designing and Evaluating Redundancy-Based Soft-Error Masking on a Continuum of Energy versus Robustness.
T-SUSC, 2018

A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency.
IEEE Trans. Emerging Topics Comput., 2018

Elevating Learner Achievement Using Formative Electronic Lab Assessments in the Engineering Laboratory: A Viable Alternative to Weekly Lab Reports.
IEEE Trans. Education, 2018

Survivability Modeling and Resource Planning for Self-Repairing Reconfigurable Device Fabrics.
IEEE Trans. Cybernetics, 2018

NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths.
IEEE Trans. Computers, 2018

Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm.
IEEE Trans. Computers, 2018

SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter leveraging SHE-enabled Domain Wall Motion devices.
Microelectronics Journal, 2018

Hybrid spin-CMOS stochastic spiking neuron for high-speed emulation of In vivo neuron dynamics.
IET Computers & Digital Techniques, 2018

Energy-Aware Adaptive Rate and Resolution Sampling of Spectrally Sparse Signals Leveraging VCMA-MTJ Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Non-Volatile Memory Trends: Toward Improving Density and Energy Profiles across the System Stack.
IEEE Computer, 2018

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization.
IEEE Access, 2018

Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile Applications.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Lockdown Computerized Testing Interwoven with Rapid Remediation: A Crossover Study within a Mechanical Engineering Core Course.
Proceedings of the IEEE Frontiers in Education Conference, 2018

2017
Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device.
IEEE Trans. VLSI Syst., 2017

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures.
IEEE Trans. Emerging Topics Comput., 2017

Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region.
IEEE Trans. on Circuits and Systems, 2017

Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures.
IEEE Trans. Computers, 2017

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache.
IEEE Trans. Computers, 2017

Towards ultra-efficient QCA reversible circuits.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency.
JETC, 2017

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods.
Integration, 2017

Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing.
IET Circuits, Devices & Systems, 2017

AI in Informal Science Education: Bringing Turing Back to Life to Perform the Turing Test.
I. J. Artificial Intelligence in Education, 2017

Secure intermittent-robust computation for energy harvesting device security and outage resilience.
Proceedings of the 2017 IEEE SmartWorld, 2017

Variation-immune resistive Non-Volatile Memory using self-organized sub-bank circuit designs.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Process variation immune and energy aware sense amplifiers for resistive non-volatile memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

RAW Keynote Speakers.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Exploring the Effect of Compiler Optimizations on the Reliability of HPC Applications.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Heterogeneous Technology Configurable Fabrics for Field-Programmable Co-Design of CMOS and Spin-Based Devices.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

A Spin-Orbit Torque based Cellular Neural Network (CNN) Architecture.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design.
IEEE Trans. on Circuits and Systems, 2016

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
IEEE Trans. Computers, 2016

Fast Online Diagnosis and Recovery of Reconfigurable Logic Fabrics Using Design Disjunction.
IEEE Trans. Computers, 2016

Intrinsic Evolution of Truncated Puiseux Series on a Mixed-Signal Field-Programmable SoC.
IEEE Access, 2016

Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Area-energy tradeoffs of logic wear-leveling for BTI-induced aging.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder.
Microelectronics Journal, 2015

ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Activity-Based Resource Allocation for Motion Estimation Engines.
Journal of Circuits, Systems, and Computers, 2015

Power and quality-aware image processing soft-resilience using online multi-objective GAs.
IJCVR, 2015

Understanding the propagation of transient errors in HPC applications.
Proceedings of the International Conference for High Performance Computing, 2015

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics.
Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hypergraph-Cover Diversity for Maximally-Resilient Reconfigurable Systems.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Self-Scaling Evolution of analog computation circuits with digital accuracy refinement.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Self-Adapting Resource Escalation for Resilient Signal Processing Architectures.
Signal Processing Systems, 2014

Passing an Enhanced Turing Test - Interacting with Lifelike Computer Representations of Specific Individuals.
J. Intelligent Systems, 2014

Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input.
Int. J. Reconfig. Comp., 2014

Sustainability assurance modeling for SRAM-based FPGA evolutionary self-repair.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Fault Demotion Using Reconfigurable Slack (FaDReS).
IEEE Trans. VLSI Syst., 2013

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms.
IEEE Trans. Computers, 2013

Self-healing reconfigurable logic using autonomous group testing.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Passing an Enhanced Turing Test - Interacting with Lifelike Computer Representations of Specific Individuals.
J. Intelligent Systems, 2013

An Extended Turing Test: A Context Based Approach Designed to Educate Youth in Computing.
Proceedings of the Modeling and Using Context, 2013

2012
Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms.
Appl. Soft Comput., 2012

Designing digital circuits for FPGAs using parallel genetic algorithms (WIP).
Proceedings of the 2012 Spring Simulation Multiconference, 2012

2011
Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption.
Int. J. Reconfig. Comp., 2011

Progress in autonomous fault recovery of field programmable gate arrays.
ACM Comput. Surv., 2011

Autonomic fault-handling and refurbishment using throughput-driven assessment.
Appl. Soft Comput., 2011

A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. VLSI Syst., 2010

Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration.
ACM Trans. Embedded Comput. Syst., 2009

A Sustainable Model for Integrating Current Topics in Machine Learning Research Into the Undergraduate Curriculum.
IEEE Trans. Education, 2009

Towards a Method For Evaluating Naturalness in Conversational Dialog Systems.
Proceedings of the IEEE International Conference on Systems, 2009

Towards a Context-Based Dialog Management Layer for Expert Systems.
Proceedings of the International Conference on Information, 2009

2008
A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration.
IEEE Trans. VLSI Syst., 2008

Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores.
Proceedings of the 2008 International Conference on Embedded Systems & Applications, 2008

2007
Tiered Algorithm for Distributed Process Quiescence and Termination Detection.
IEEE Trans. Parallel Distrib. Syst., 2007

Pipelining of Fuzzy ARTMAP without matchtracking: Correctness, performance bound, and Beowulf evaluation.
Neural Networks, 2007

Self-Timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion.
Journal of Circuits, Systems, and Computers, 2007

Evaluation of Distributed File Integrity Analyzers in the Presence of Tampering.
I. J. Network Security, 2007

Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices.
Proceedings of the FPL 2007, 2007

Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
Learning tactical human behavior through observation of human performance.
IEEE Trans. Systems, Man, and Cybernetics, Part B, 2006

Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integration, 2006

Mitigation of Insider Risks using Distributed Agent Detection, Filtering, and Signaling.
I. J. Network Security, 2006

CONFIDANT: Collaborative Object Notification Framework for Insider Defense using Autonomous Network Transactions.
Autonomous Agents and Multi-Agent Systems, 2006

A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

A combinatorial group testing method for FPGA fault location.
Proceedings of the IASTED International Conference on Advances in Computer Science and Technology, 2006

2005
Data-partitioning using the Hilbert space filling curves: Effect on the speed of convergence of Fuzzy ARTMAP for large database problems.
Neural Networks, 2005

Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Self-Checking Fault Detection using Discrepancy Mirrors.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Consensus-Based Evaluation for Fault Isolation and On-line Evolutionary Regeneration.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2005

A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Autonomous FPGA Fault Handling through Competitive Runtime Reconfiguration.
Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005

2004
Smart priority queue algorithms for self-optimizing event storage.
Simulation Modelling Practice and Theory, 2004

Optimization of NULL convention self-timed circuits.
Integration, 2004

Evaluation of the Human Impact of Password Authentication.
InformingSciJ, 2004

Mitigation of network tampering using dynamic dispatch of mobile agents.
Computers & Security, 2004

A Partitioned Fuzzy ARTMAP Implementation for Fast Processing of Large Databases on Sequential Machines.
Proceedings of the Seventeenth International Florida Artificial Intelligence Research Society Conference, 2004

Feedback Techniques for Dual-Rail Self-Timed Circuits.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
Distributed-sum termination detection supporting multithreaded execution.
Parallel Computing, 2003

CRCD in machine learning at the University of Central Florida preliminary experiences.
Proceedings of the 8th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2003

High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003

2002
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.
Journal of Systems Architecture, 2002

Communication Pattern Based Methodology for Performance Analysis of Termination Detection Schemes.
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002

2001
Delay-insensitive gate-level pipelining.
Integration, 2001

A Connectionist-Symbolic Approach to Modeling Agent Behavior: Neural Networks Grouped by Contexts.
Proceedings of the Modeling and Using Context, 2001

2000
Performance of Scalabale Shared-Memory Architectures.
Journal of Circuits, Systems, and Computers, 2000

1994
Barrier Synchronization Techniques for Distributed Process Creation.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

1993
A Parallel Computational Model for Integrated Speech and Natural Language Understanding.
IEEE Trans. Computers, 1993

1991
Marker-Passing on a Parallel Knowledge Processing Testbed.
Proceedings of the First International Conference on Parallel and Distributed Information Systems (PDIS 1991), 1991

The SNAP-1 Parallel AI Prototype.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Design of a Clustered Multiprocessor for Real-time Natural Language Understanding.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

Performance Indices for Parallel Marker-Propagation.
Proceedings of the International Conference on Parallel Processing, 1991


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