Ahmed H. Khalil

According to our database1, Ahmed H. Khalil authored at least 15 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Mobile Aerial Base Stations for Ultra-Reliable and Energy-Efficient Downlink Communications.
Proceedings of the IEEE International Conference on Smart Mobility, 2023

Mini-YOLOX: A Lightweight Network for Real-Time Embedded Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

SoC-Oriented Implementation of Machine Learning Based Breast Cancer Classification Algorithm.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2021
Design of a reconfigurable network-on-chip for next generation FPGAs using Dynamic Partial Reconfiguration.
Microelectron. J., 2021

Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet.
IEEE Access, 2021

Low Power, Dual Mode Bluetooth 5.1/Bluetooth Low Energy Receiver Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Efficient HLS Implementation for Convolutional Neural Networks Accelerator on an SoC.
Proceedings of the International Conference on Microelectronics, 2021

Fast RTL Implementation of A* Path Planning Algorithm.
Proceedings of the International Conference on Microelectronics, 2021

2018
Dynamic power estimation using Transaction Level Modeling.
Microelectron. J., 2018

A Software Defined Radio Transceiver Based on Dynamic Partial Reconfiguration.
Proceedings of the 2018 New Generation of CAS, 2018

Multi-Bit RRAM Transient Modelling and Analysis.
Proceedings of the 30th International Conference on Microelectronics, 2018

Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2013
Testing of N-stage pipelined ADC using test input regeneration and sliding window techniques.
Proceedings of the Third International Conference on Communications and Information Technology, 2013

2012
An accurate power delivery system (PDS) design methodology for high-speed digital systems.
Int. J. Circuit Theory Appl., 2012

2007
Design and Implementation of FPGA-based Systolic Array for LZ Data Compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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