Ahmed J. Abd El-Maksoud

Cristian Sestito

Shiwei Wang

CoRR, February, 2026

DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration.

[BibT_eX]

[DOI]

Shady Agwa

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026

2025

ADiP: Adaptive Precision Systolic Array for Matrix Multiplication Acceleration.

[BibT_eX]

[DOI]

Cristian Sestito

Shiwei Wang

CoRR, October, 2025

3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads.

[BibT_eX]

[DOI]

Cristian Sestito

Shady Agwa

CoRR, February, 2025

2021

Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet.

[BibT_eX]

[DOI]

Mohamed Ebbed

Ahmed Hussein Khalil

Hassan Mostafa

IEEE Access, 2021

FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 3rd Novel Intelligent and Leading Emerging Sciences Conference, 2021

Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Microelectronics, 2021

2019

FPGA implementation of sound encryption system based on fractional-order chaotic systems.

[BibT_eX]

[DOI]

Mohamed Fathy Abu-ElYazeed

Ayman A. Abd El-Kader

Microelectron. J., 2019

2018

ASIC Oriented Comparative Analysis Of Biologically Inspired Neuron Models.

[BibT_eX]

[DOI]

Youssef O. Elmasry

Khaled N. Salama

Hassan Mostafa

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

FPGA implementation of fractional-order Chua's chaotic system.

[BibT_eX]

[DOI]