Ajay K. Verma

According to our database1, Ajay K. Verma authored at least 36 papers between 2004 and 2019.

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Bibliography

2019
EEG-based Classification of Microsleep by Means of Feature Selection: An Application in Aviation.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019

2018
Early Identification of Bleeding: Past Achievement, Current Limitations & Future Development.
Proceedings of the 2018 IEEE International Conference on Electro/Information Technology, 2018

2017
Challenges in Using Seismocardiography for Blood Pressure Monitoring.
Proceedings of the Computing in Cardiology, 2017

2016
Analysis of causal cardio-postural interaction under orthostatic stress using convergent cross mapping.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Preliminary results of residual deficits observed in athletes with concussion history: Combined EEG and cognitive study.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Causality detection in cardio-postural interaction under orthostatic stress induced by quiet standing using transfer entropy.
Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

A review of methods and applications of brain computer interface systems.
Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

Heart Sound Classification from Wavelet Decomposed Signal Using Morphological and Statistical Features.
Proceedings of the Computing in Cardiology, CinC 2016, Vancouver, 2016

Increased Systolic Blood Pressure driven Skeletal Muscle activation Following Stroke: A causality analysis.
Proceedings of the Computing in Cardiology, CinC 2016, Vancouver, 2016

2015
Causality in the Cardio-Postural Interactions During Quiet Stance.
Proceedings of the Computing in Cardiology, 2015

Pulse Transit Time Extraction from Seismocardiogram and its Relationship with Pulse Pressure.
Proceedings of the Computing in Cardiology, 2015

2010
Improving FPGA Performance for Carry-Save Arithmetic.
IEEE Trans. VLSI Syst., 2010

Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.
TRETS, 2009

Optimistic chordal coloring: a coalescing heuristic for SSA form programs.
Design Autom. for Emb. Sys., 2009

Arithmetic optimization for custom instruction set synthesis.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Iterative layering: Optimizing arithmetic circuits by structuring the information flow.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Hybrid LZA: a near optimal implementation of the leading zero anticipator.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Challenges in Automatic Optimization of Arithmetic Circuits.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.
Proceedings of the Design, Automation and Test in Europe, 2008

Fast, quasi-optimal, and pipelined instruction-set extensions.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automatic synthesis of compressor trees: reevaluating large counters.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Enhancing FPGA Performance for Arithmetic Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Rethinking custom ISE identification: a new processor-agnostic method.
Proceedings of the 2007 International Conference on Compilers, 2007

An optimistic and conservative register assignment heuristic for chordal graphs.
Proceedings of the 2007 International Conference on Compilers, 2007

Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Towards the automatic exploration of arithmetic-circuit architectures.
Proceedings of the 43rd Design Automation Conference, 2006

2004
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Arithmetic Transformations to Maximise the Use of Compressor Trees.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004


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