Alec Aversa

Orcid: 0000-0001-9432-5073

According to our database1, Alec Aversa authored at least 5 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2025
Deep Representation Learning for Electronic Design Automation.
CoRR, May, 2025

Avoiding Malicious Nodes of a 3-D NoC with Security-Aware Priority-Based Routing.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

TARN: Trust Aware Routing to Enhance Security in 3D Network-on-Chips.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Harnessing Heterogeneity for Targeted Attacks on 3-D ICs.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024


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