Ioannis Savidis

According to our database, Ioannis Savidis authored at least 78 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Hidden Costs of Analog Deobfuscation Attacks.

Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation.

Zhengfeng Wu, Isabel Song, Ioannis Savidis

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies.

Zhengfeng Wu, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect.

Pratik Shrestha, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Power Side-Channel Attack on Flash ADC.

Ziyi Chen, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks.

Zhengfeng Wu, Ioannis Savidis

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Graph Representation Learning for Gate Arrival Time Prediction.

Pratik Shrestha, Saran Phatharodom, Ioannis Savidis

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits.

Vaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Adaptive-Gravity: A Defense Against Adversarial Samples.

Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes.

Zhengfeng Wu, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking.

Pratik Shrestha, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Reconfigurable Analog Array for Hardware Security.

Ziyi Chen, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Practical Performance of Analog Attack Techniques.

Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.

Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Sayed Aresh Beheshti-Shirazi, Ali Mirzaeian, Xiaojie Guo, Sai Manoj P. D., Houman Homayoun, Ioannis Savidis, Liang Zhao, Avesta Sasan

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Performance and Security Analysis of Parameter-Obfuscated Analog Circuits.

Vaibhav Venugopal Rao, Ioannis Savidis

IEEE Trans. Very Large Scale Integr. Syst., 2021

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking.

Kyle Juretus, Ioannis Savidis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Synthesis of Hidden State Transitions for Sequential Logic Locking.

Kyle Juretus, Ioannis Savidis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators.

Md Shazzad Hossain, Ioannis Savidis

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Variation-aware Analog Circuit Sizing with Classifier Chains.

Zhengfeng Wu, Ioannis Savidis

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Reconfigurable Array for Analog Applications.

Ziyi Chen, Ioannis Savidis

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

SAT-attack Resilience Measure for Access Restricted Circuits.

Saran Phatharodom, Avesta Sasan, Ioannis Savidis

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop.

Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj P. D., Ioannis Savidis, Houman Homayoun, Avesta Sasan

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Energy Efficient Computing with Heterogeneous DNN Accelerators.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack.

Kyle Juretus, Ioannis Savidis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing.

Md Shazzad Hossain, Ioannis Savidis

Microelectron. J., 2020

Recycling of unused leakage current for energy efficient multi-voltage systems.

Md Shazzad Hossain, Ioannis Savidis

Microelectron. J., 2020

Physical Layer Encryption for Wireless OFDM Communication Systems.

Marko Jacovic, Kyle Juretus, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar

J. Hardw. Syst. Secur., 2020

CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing.

Zhengfeng Wu, Ioannis Savidis

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Dynamic idle core management and leakage current reuse in MPSoC platforms.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Security Vulnerabilities of Obfuscated Analog Circuits.

Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Modeling SAT-Attack Search Complexity.

Saran Phatharodom, Nagarajan Kandasamy, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reducing Logic Locking Key Leakage through the Scan Chain.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber

IEEE Trans. Very Large Scale Integr. Syst., 2019

Securing Wireless Communication via Hardware-Based Packet Obfuscation.

James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar

J. Hardw. Syst. Secur., 2019

Robust Low Power Clock Synchronization for Multi-Die Systems.

Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Mesh Based Obfuscation of Analog Circuit Properties.

Vaibhav Venugopal Rao, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Increasing the SAT Attack Resiliency of In-Cone Logic Locking.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Applying Swarm Intelligence to Distributed On-Chip Power Management.

Divya Pathak, Ioannis Savidis

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies.

Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.

Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun

IEEE Trans. Very Large Scale Integr. Syst., 2018

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors.

Divya Pathak, Ioannis Savidis

IEEE Trans. Very Large Scale Integr. Syst., 2018

Time Domain Sequential Locking for Increased Security.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Noise Constrained Optimum Selection of Supply Voltage for IoT Applications.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures.

David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Securing the Systems of the Future - Techniques for a Shifting Attack Space.

Ioannis Savidis, Swarup Bhunia, Gang Qu, Matthew J. Casto, Jeremy Muldavin

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning.

Hossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory.

Vaibhav Venugopal Rao, Ioannis Savidis

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security.

Kyle Juretus, Ioannis Savidis

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery.

Divya Pathak, Houman Homayoun, Ioannis Savidis

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson

IEEE Trans. Very Large Scale Integr. Syst., 2017

Clock tree synthesis for heterogeneous 3-D integrated circuits.

Isuru Daulagala, Ioannis Savidis

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Bi-directional input/output circuits with integrated level shifters for near-threshold computing.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Protecting analog circuits with parameter biasing obfuscation.

Vaibhav Venugopal Rao, Ioannis Savidis

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Physical gate based preamble obfuscation for securing wireless communication.

James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar

Proceedings of the 2017 International Conference on Computing, 2017

Parameter biasing obfuscation for analog IP protection.

Vaibhav Venugopal Rao, Ioannis Savidis

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery.

Divya Pathak, Houman Homayoun, Ioannis Savidis

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.

Ioannis Savidis, Berkehan Ciftcioglu, Jie Xu, Jianyun Hu, Manish Jain, Rebecca Berman, Jing Xue, Peng Liu, Duncan Moore, Gary Wicks, Michael C. Huang, Hui Wu, Eby G. Friedman

Microelectron. J., 2016

A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures.

Kostas Siozios, Ioannis Savidis, Dimitrios Soudris

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Energy efficient on-chip power delivery with run-time voltage regulator clustering.

Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reducing logic encryption overhead through gate level key insertion.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Robust near-threshold inverter with improved performance for ultra-low power applications.

Md Shazzad Hossain, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Load Balanced On-Chip Power Delivery for Average Current Demand.

Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Reduced Overhead Gate Level Logic Encryption.

Kyle Juretus, Ioannis Savidis

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits.

Ioannis Savidis, Boris Vaisband, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 2015

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.

Mohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis, Houman Homayoun

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.

Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Run-time voltage detection circuit for 3-D IC power delivery.

Divya Pathak, Ioannis Savidis

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Thermal conduction path analysis in 3-D ICs.

Boris Vaisband, Ioannis Savidis, Eby G. Friedman

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Power Noise in TSV-Based 3-D Integrated Circuits.

Ioannis Savidis, Selçuk Köse, Eby G. Friedman

IEEE J. Solid State Circuits, 2013

2011

Clock Distribution Networks in 3-D Integrated Systems.

Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 2011

Thermal analysis of oxide-confined VCSEL arrays.

Jinhui Wang, Ioannis Savidis, Eby G. Friedman

Microelectron. J., 2011

Clock distribution models of 3-D integrated systems.

Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits.

Ioannis Savidis, Syed M. Alam, Ankur Jain, Scott Pozder, Robert E. Jones, Ritwik Chatterjee

Microelectron. J., 2010

An intra-chip free-space optical interconnect.

Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2008

Electrical modeling and characterization of 3-D vias.

Ioannis Savidis, Eby G. Friedman

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Clock distribution networks for 3-D ictegrated Circuits.

Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008