Naghmeh Karimi

Suhee Sanjana Mehjabin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

The 28th IEEE European Test Symposium.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2024

Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

Digital Twin Integrity Protection in Distributed Control Systems.

[BibT_eX]

[DOI]

Mohamed Younis

Proceedings of the 21st IEEE Consumer Communications & Networking Conference, 2024

2023

The 41st IEEE VLSI Test Symposium.

[BibT_eX]

[DOI]

IEEE Des. Test, October, 2023

A Networked System Dependability Validation Framework Using Physical and Virtual Nodes.

[BibT_eX]

[DOI]

Suhee Sanjana Mehjabin

Ali Tekeoglu

Rahul Chandran

Tamim Sookoor

IEEE Access, 2023

Special Session: Security Verification & Testing for SR-Latch TRNGs.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

International Mutual Recognition: A Description of Trust Services in US, UK, EU and JP and the Testbed "Hakoniwa".

[BibT_eX]

[DOI]

Satoshi Kai

Takao Kondo

Konstantinos Mersinas

Marc Sel

Roberto Yus

Satoru Tezuka

Proceedings of the 20th International Conference on Security and Cryptography, 2023

Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2023

Security Order of Gate-Level Masking Schemes.

[BibT_eX]

[DOI]

Sofiane Takarabt

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Aging-Induced Failure Prognosis via Digital Sensors.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Welcome Message from the Chairs.

[BibT_eX]

[DOI]

Farshad Firouzi

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

2022

Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Countering Modeling Attacks in PUF-based IoT Security Solutions.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

A PUF-Based Modeling-Attack Resilient Authentication Protocol for IoT Devices.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2022

Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs.

[BibT_eX]

[DOI]

J. Electron. Test., 2022

Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

An Attack Resilient PUF-based Authentication Mechanism for Distributed Systems.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Security and Cryptography, 2022

Does Aging Matter? The Curious Case of Fault Sensitivity Analysis.

[BibT_eX]

[DOI]

Bijan Fadaeinia

Amir Moradi

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Detecting Laser Fault Injection Attacks via Time-to-Digital Converter Sensors.

[BibT_eX]

[DOI]

Suhee Sanjana Mehjabin

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

SWeeT: Security Protocol for Wearables Embedded Devices' Data Transmission.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on E-health Networking, 2022

Collusion-resistant PUF-based Distributed Device Authentication Protocol for Internet of Things.

[BibT_eX]

[DOI]

Mohamed Younis

Proceedings of the IEEE Global Communications Conference, 2022

Leakage Power Analysis in Different S-Box Masking Protection Schemes.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Robust and Efficient Data Security Solution for Pervasive Data Sharing in IoT.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022

2021

Detecting Failures and Attacks via Digital Sensors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Reducing Aging Impacts in Digital Sensors via Run-Time Calibration.

[BibT_eX]

[DOI]

Md Toufiq Hasan Anik

J. Electron. Test., 2021

Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security.

[BibT_eX]

[DOI]

Xingyu Meng

Kanad Basu

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

AVATAR: NN-Assisted Variation Aware Timing Analysis and Reporting for Hardware Trojan Detection.

[BibT_eX]

[DOI]

IEEE Access, 2021

Masked SABL: A Long Lasting Side-Channel Protection Design Methodology.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Novel Modeling-Attack Resilient Arbiter-PUF Design.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Real-Time IC Aging Prediction via On-Chip Sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Countering PUF Modeling Attacks through Adversarial Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Hardware Assisted Smart Grid Authentication.

[BibT_eX]

[DOI]

Proceedings of the ICC 2021, 2021

Testing and Reliability Enhancement of Security Primitives.

[BibT_eX]

[DOI]

Md Toufiq Hasan Anik

Omar Diankha

Sai Manoj Pudukotai Dinakarrao

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Enhancing the Resiliency of Multi-bit Parallel Arbiter-PUF and Its Derivatives Against Power Attacks.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2021

Learning Assisted Side Channel Delay Test for Detection of Recycled ICs.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain.

[BibT_eX]

[DOI]

Shervin Roshanisefat

Hadi Mardani Kamali

Kimia Zamiri Azar

Houman Homayoun

Avesta Sasan

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

On the Effect of Aging on Digital Sensors.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability.

[BibT_eX]

[DOI]

Md Toufiq Hasan Anik

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Failure and Attack Detection by Digital Sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Effect of Aging on PUF Modeling Attacks based on Power Side-Channel Observations.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Real-Time Prediction for IC Aging Based on Machine Learning.

[BibT_eX]

[DOI]

Ke Huang

Xinqiao Zhang

IEEE Trans. Instrum. Meas., 2019

Exploring the Effect of Device Aging on Static Power Analysis Attacks.

[BibT_eX]

[DOI]

Jeyavijayan (JV) Rajendran

Thorben Moos

Amir Moradi

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Implementation-Based Design Fingerprinting for Robust IC Fraud Detection.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2019

Special Session: Countering IP Security threats in Supply chain.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Impact of Aging on the Reliability of Delay PUFs.

[BibT_eX]

[DOI]

J. Electron. Test., 2018

Special session: Recent developments in hardware security.

[BibT_eX]

[DOI]

Ro Cammarota

Siddharth Garg

Jeyavijayan Rajendran

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Impact of Aging on Template Attacks.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Device aging: A reliability and security concern.

[BibT_eX]

[DOI]

Hans-Joachim Wunderlich

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

Predictive Aging of Reliability of two Delay PUFs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Impact of the switching activity on the aging of delay-PUFs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Prognosis of NBTI aging using a machine learning scheme.

[BibT_eX]

[DOI]

Ke Huang

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015

Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

MAGIC: Malicious Aging in Circuits/Cores.

[BibT_eX]

[DOI]

Arun Karthik Kanuparthi

Xueyang Wang

Ozgur Sinanoglu

Ramesh Karri

ACM Trans. Archit. Code Optim., 2015

Exploiting small leakages in masks to turn a second-order attack into a first-order attack.

[BibT_eX]

[DOI]

Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Simulation and analysis of negative-bias temperature instability aging on power analysis attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2014

Detection, diagnosis, and repair of faults in memristor-based memories.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Secure Memristor-based Main Memory.

[BibT_eX]

[DOI]

Sachhidh Kannan

Ozgur Sinanoglu

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On the Impact of Performance Faults in Modern Microprocessors.

[BibT_eX]

[DOI]

Chandrasekharan Tirumurti

Michail Maniatakos

Yiorgos Makris

J. Electron. Test., 2013

Special session 4B: Elevator talks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Reconciling the IC test and security dichotomy.

[BibT_eX]

[DOI]

Ozgur Sinanoglu

Jeyavijayan Rajendran

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

Test generation for clock-domain crossing faults in integrated circuits.

[BibT_eX]

[DOI]

Pallav Gupta

Srinivas Patil

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.

[BibT_eX]

[DOI]

Zhiqiu Kong

Pallav Gupta

Srinivas Patil

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009

Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Impact analysis of performance faults in modern microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

2008

Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2008

On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Reliable NoC architecture utilizing a robust rerouting algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2008 East-West Design & Test Symposium, 2008

Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

RT level reliability enhancement by constructing dynamic TMRS.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs.

[BibT_eX]

[DOI]