Alexander J. Leigh
Orcid: 0000-0002-9098-4650
  According to our database1,
  Alexander J. Leigh
  authored at least 12 papers
  between 2018 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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    on orcid.org
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Bibliography
  2025
    Proceedings of the 16th IEEE Latin America Symposium on Circuits and Systems, 2025
    
  
  2024
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2<sup>m</sup>).
    
  
    IEEE Trans. Very Large Scale Integr. Syst., August, 2024
    
  
  2023
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., October, 2023
    
  
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., September, 2023
    
  
Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
    
  
  2022
Hardware Implementations of Spiking Neural Networks and Artificially Intelligent Systems.
    
  
    PhD thesis, 2022
    
  
A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2022
    
  
    Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
    
  
  2020
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
    
  
  2019
    IEEE Trans. Circuits Syst. II Express Briefs, 2019
    
  
  2018
Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2018