Mohammed A. S. Khalid

Mitra Mirhassani

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

2022

An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic.

[BibT_eX]

[DOI]

Madhan Thirumoorthi

Moslem Heidarpur

Mitra Mirhassani

IEEE Trans. Very Large Scale Integr. Syst., 2022

Automated Generation and Integration of AUTOSAR RTE Configurations.

[BibT_eX]

[DOI]

Shawn Smith

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2022

2021

Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF.

[BibT_eX]

[DOI]

Madhan Thirumoorthi

Marko Jovanovic

Mitra Mirhassani

IEEE Trans. Very Large Scale Integr. Syst., 2021

Latency-optimised 3D multi-FPGA system with serial optical interface.

[BibT_eX]

[DOI]

Asmeen Kashif

Int. J. Comput. Aided Eng. Technol., 2021

2020

Experimental evaluation and comparison of latency-optimized opticaland conventional multi-FPGA systems.

[BibT_eX]

[DOI]

Asmeen Kashif

Des. Autom. Embed. Syst., 2020

A Study on Extreme Learning Machine for Gasoline Engine Torque Prediction.

[BibT_eX]

[DOI]

Weiying Zeng

Xiaoye Han

Jimi Tjong

IEEE Access, 2020

FPGA-Based Evaluation and Implementation of an Automotive RADAR Signal Processing System using High-Level Synthesis.

[BibT_eX]

[DOI]

Siddhant Luthra

Mohammad Abdul Moin Oninda

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2020

2019

FPGA-Based Acceleration of Expectation Maximization Algorithm Using High-Level Synthesis.

[BibT_eX]

[DOI]

Mohammad Abdul Momen

Mohammad Abdul Moin Oninda

Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

2018

An FPGA-based controller for a 77 GHz MEMS tri-mode automotive radar.

[BibT_eX]

[DOI]

Sabrina Zereen

Sundeep Lal

Microprocess. Microsystems, 2018

Acceleration of k-Nearest Neighbor Algorithm on FPGA using Intel SDK for OpenCL.

[BibT_eX]

[DOI]

Liyuan Liu

Jenita Priya Rajamanickam Manokaran

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Variable tap-length algorithm using lattice structured LMS adaptive filters.

[BibT_eX]

[DOI]

Salem Alsaid

Khaled Mayyas

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016

Acceleration of k-Means Algorithm Using Altera SDK for OpenCL.

[BibT_eX]

[DOI]

Qing Y. Tang

ACM Trans. Reconfigurable Technol. Syst., 2016

In-Vehicle Networks Outlook: Achievements and Challenges.

[BibT_eX]

[DOI]

Weiying Zeng

IEEE Commun. Surv. Tutorials, 2016

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures.

[BibT_eX]

[DOI]

Asmeen Kashif

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL.

[BibT_eX]

[DOI]

Ian Janik

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only).

[BibT_eX]

[DOI]

Sabrina Zereen

Sundeep Lal

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

A qualitative comparison of FlexRay and Ethernet in vehicle networks.

[BibT_eX]

[DOI]

Weiying Zeng

Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

An overview of Altera SDK for OpenCL: A user perspective.

[BibT_eX]

[DOI]

Ian Janik

Qing Y. Tang

Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

2014

A Parameterizable NoC Router for FPGAs.

[BibT_eX]

[DOI]

Mike Brugge

J. Comput., 2014

Control Mechanism to Solve False Blocking Problem at MAC Layer in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Brajendra Kumar Singh

Kemal E. Tepe

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Configurable hardware implementation of a pipelined DNLMS adaptive filter.

[BibT_eX]

[DOI]

Raymond Lee

Proceedings of the 26th International Conference on Microelectronics, 2014

2013

FPGA based wireless sensor node with customizable event-driven architecture.

[BibT_eX]

[DOI]

Junsong Liao

Brajendra Kumar Singh

Kemal E. Tepe

EURASIP J. Embed. Syst., 2013

FLNR: A fast light-weight NoC router for FPGAs.

[BibT_eX]

[DOI]

Abdelrazag Imbewa

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2011

A novel simplified Log-MAP algorithm suitable for hardware implementation of turbo decoding.

[BibT_eX]

[DOI]

Krishnamohan Thangarajah

Behnam Shahrrava

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010

Design and evaluation of a parameterizable NoC router for FPGAs (abstract only).

[BibT_eX]

[DOI]

Mike Brugge

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009

SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays.

[BibT_eX]

[DOI]

Ian D. L. Anderson

IET Comput. Digit. Tech., 2009

Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications.

[BibT_eX]

[DOI]

Linlin Zhang

Virginie Fresse

Dominique Houzet

Anne-Claire Legrand

EURASIP J. Embed. Syst., 2009

GALS NoC architectures on FPGA dedicated to multispectral image applications.

[BibT_eX]

[DOI]

Linlin Zhang

Virginie Fresse

Anne-Claire Legrand

Proceedings of the 17th European Signal Processing Conference, 2009

UWindsor Nios II: A soft-core processor for design space exploration.

[BibT_eX]

[DOI]

Omar A. Al Rayahi

Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009

2008

A Fast and Effective Timing-Driven Placement Tool for FPGAS.

[BibT_eX]

[DOI]

Yonghong Xu

J. Circuits Syst. Comput., 2008

Profiling Tools for FPGA-Based Embedded Systems: Survey and Quantitative Comparison.

[BibT_eX]

[DOI]

Jason G. Tong

J. Comput., 2008

2007

A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators.

[BibT_eX]

[DOI]

Kevin Banovic

Digit. Signal Process., 2007

2006

A novel radius-adjusted approach for blind adaptive equalization.

[BibT_eX]

[DOI]

Kevin Banovic

IEEE Signal Process. Lett., 2006

Computationally-Efficient DNLMS-Based Adaptive Algorithms for Echo Cancellation Application.

[BibT_eX]

[DOI]

Raymond Lee

J. Commun., 2006

Design Space Exploration using Parameterized Cores: A Case Study.

[BibT_eX]

[DOI]

Ian D. L. Anderson

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005

Hybrid Methods for Blind Adaptive Equalization: New Results and Comparisons.

[BibT_eX]

[DOI]

Kevin Banovic

Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 2005

QPF: Efficient Quadratic Placement for FPGAs.

[BibT_eX]

[DOI]

Yonghong Xu

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2000

A novel and efficient routing architecture for multi-FPGA systems.

[BibT_eX]

[DOI]

Jonathan Rose

IEEE Trans. Very Large Scale Integr. Syst., 2000

1999

Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Jonathan Rose

Proceedings of the Parallel and Distributed Processing, 1999

1998

A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.

[BibT_eX]

[DOI]