Mitra Mirhassani
Orcid: 0000-0001-8512-6427
According to our database1,
Mitra Mirhassani
authored at least 60 papers
between 2003 and 2023.
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Bibliography
2023
Developing a fuzzy optimized model for selecting a maintenance strategy in the paper industry: An integrated FGP-ANP-FMEA approach.
Expert Syst. Appl., December, 2023
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation".
IEEE Trans. Very Large Scale Integr. Syst., 2022
A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference.
Microelectron. J., 2021
2020
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model.
IEEE Trans. Circuits Syst., 2020
2019
A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Access, 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Neurocomputing, 2017
Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amps.
IET Circuits Devices Syst., 2017
A neural network architecture using high resolution multiplying digital to analog converters.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
Efficient mixed-signal synapse multipliers for multi-layer feed-forward neural networks.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
2014
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Neurocomputing, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the ISMVL 2009, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2003
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays.
Proceedings of the International Conference on VLSI, 2003