Alfonso Chacón-Rodríguez

Orcid: 0000-0002-9094-8983

According to our database1, Alfonso Chacón-Rodríguez authored at least 24 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices.
IEEE Embed. Syst. Lett., June, 2023

2022
A custom interconnection multi-FPGA framework for distributed processing applications.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

2021
PlasticNet+: Extending Multi-FPGA Interconnect Architecture via Gigabit Transceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications.
Microelectron. J., 2020

SoC-FPGA Implementation of a Temperature-Dependent Parameters Estimator for Photovoltaic Generators.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

An IC Mixed-Signal Framework for Design, Optimization, and Verification of High-Speed Links.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020


A RISC-V Based Medical Implantable SoC for High Voltage and Current Tissue Stimulus.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Integrated Programmable Current Source for Implantable Medical Devices.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Triggers for Irrigation Decision-Making in Greenhouse Horticulture using Internet of Things.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
An asymmetrical bulk-modified composite MOS transistor with enhanced linearity.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Prototyping a Biologically Plausible Neuron Model on a Heterogeneous CPU-FPGA Board.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Optimizing Big Data Network Transfers in FPGA SoC Clusters: TECBrain Case Study.
Proceedings of the High Performance Computing - 6th Latin American Conference, 2019

Improving the Simulation of Biologically Accurate Neural Networks Using Data Flow HLS Transformations on Heterogeneous SoC-FPGA Platforms.
Proceedings of the High Performance Computing - 6th Latin American Conference, 2019

2017
A 0.13 CMOS integrated circuit for electrical impedance spectroscopy from 1 kHz to 10 GHz.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

RISC-V based sound classifier intended for acoustic surveillance in protected natural environments.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2015
Digital integrated circuit implementation of an identification stage for the detection of illegal hunting and logging.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Analysis of source separation algorithms in industrial acoustic environments.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2011
Evaluation of Gunshot Detection Algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2009
A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2007
A comparison of low power architectures for digital delay measurement.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


  Loading...