Pablo Sergio Mandolesi

According to our database1, Pablo Sergio Mandolesi authored at least 26 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Distortion-Free All-Digital Transmitter Based on Noise-Shaped PWM.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

2022
Low Power 18-Bit PWM With 41 ps Resolution in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2020
Baseband Model for Uniformly Sampled RF-PWM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A high-resolution all-digital pulse-width modulator architecture with a tunable delay element in CMOS.
Int. J. Circuit Theory Appl., 2020

2019
Table-based PWM for all-digital RF transmitters.
Int. J. Circuit Theory Appl., 2019

2017
Blind range level shifters from 0 to 18 V.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2015
A safe MOSFET driver for stimulation of biological tissue.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014
SCDVP: A Simplicial CNN Digital Visual Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
Diagnose of radiation induced single event effects in a PLL using a heavy ion microbeam.
Proceedings of the 14th Latin American Test Workshop, 2013

Fully integrated single-inductor multiple-output (SIMO) DC-DC converter in CMOS 65 nm technology.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A dual core low power microcontroller with openMSP430 architecture for high reliability lockstep applications using a 180 nm high voltage technology node.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
Joint sampling-time error and channel skew calibration of time-interleaved ADC in multichannel fiber optic receivers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010
Carbon Nanotube Integration with a CMOS Process.
Sensors, 2010

PWL cores for nonlinear array processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Radiation damage characterization of digital integrated circuits.
Proceedings of the 10th Latin American Test Workshop, 2009

2007
A comparison of low power architectures for digital delay measurement.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A simplicial CNN visual processor in 3D SOI-CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Hybrid sensor network and fusion algorithm for sound source localization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Field test results for low power bearing estimator sensor nodes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A scalable and programmable simplicial CNN digital pixel processor architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A simplicial CNN architecture for on-chip image processing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A low-power CMOS integrated circuit for bearing estimation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1997
Fast inner-outer point evaluation in a polytopic generalization domain.
Proceedings of International Conference on Neural Networks (ICNN'97), 1997


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