Ali Asghar Vatanjou

Orcid: 0000-0002-9561-2768

According to our database1, Ali Asghar Vatanjou authored at least 9 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018
Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing.
Microprocess. Microsystems, 2018

2017
Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI.
Microprocess. Microsystems, 2017

2016
Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block.
Proceedings of the 2016 MIXDES, 2016

2015
Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI.
Proceedings of the Nordic Circuits and Systems Conference, 2015

4 Sub-/near-threshold flip-flops with application to frequency dividers.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Modular layout-friendly cell library design applied for subthreshold CMOS.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014


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