Snorre Aunet

According to our database1, Snorre Aunet authored at least 80 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2021
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode.
J. Signal Process. Syst., 2021

2020
Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping.
IEEE Trans. Very Large Scale Integr. Syst., 2020

An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V.
IEEE Trans. Circuits Syst., 2020

Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2019
An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

2018
Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing.
Microprocess. Microsystems, 2018

A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology.
Integr., 2018

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017
Special issue: Selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): Norchip & International Symposium on System-on-Chip (SoC)).
Microprocess. Microsystems, 2017

Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI.
Microprocess. Microsystems, 2017

2016
Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block.
Proceedings of the 2016 MIXDES, 2016

2015
Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI.
Proceedings of the Nordic Circuits and Systems Conference, 2015

An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm.
Proceedings of the Nordic Circuits and Systems Conference, 2015

4 Sub-/near-threshold flip-flops with application to frequency dividers.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Modular layout-friendly cell library design applied for subthreshold CMOS.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2013
A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.
IEEE J. Solid State Circuits, 2013

Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devices.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Yield-oriented energy and performance model for subthreshold circuits with Vth variations.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process.
Microprocess. Microsystems, 2011

Multi-objective optimization of minority-3 functions for ultra-low voltage supplies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

On the reliability of ultra low voltage circuits built from minority-3 gates.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Muller C-elements based on minority-3 functions for ultra low voltage supplies.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Statistical Simulations on Perceptron-Based Adders.
Proceedings of the Encyclopedia of Artificial Intelligence (3 Volumes), 2009

Synthetic Neuron Implementations.
Proceedings of the Encyclopedia of Artificial Intelligence (3 Volumes), 2009

New subthreshold concepts in 65nm CMOS technology.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Ultra Low Power Full Adder Topologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Real-Time Reconfigurable Subthreshold CMOS Perceptron.
IEEE Trans. Neural Networks, 2008

Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.
J. Electron. Test., 2008

65NM sub-threshold 11T-SRAM for ultra low voltage applications.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

High Speed Ultra Low Voltage CMOS inverter.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Clocked semi-floating-gate ultra low-voltage current mirror.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Ultra low voltage and, nor and XOR CMOS gates.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

High speed and ultra low voltage CMOS latch.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
Serial Addition: Locally Connected Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits.
Proceedings of the Computational and Ambient Intelligence, 2007

Fault Tolerant CMOS Logic Using Ternary Gates.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Band Pass Pseudo Floating-Gate Amplifier.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Pseudo Floating-Gate Inverter with Feedback Control.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Body-bias regulator for ultra low power multifunction CMOS gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Ultra low voltage CMOS gates.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Femto Joule Switching for Nano Electronics.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2005
Using Kolmogorov Inspired Gates for Low Power Nanoelectronics.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

On the Advantages of Serial Architectures for Low-Power Reliable Computations.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Basic Multiple-Valued Functions Using Recharge CMOS Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003
Erratum to "real-time reconfigurable linear threshold elements implemented in floating-gate CMOS".
IEEE Trans. Neural Networks, 2003

Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS.
IEEE Trans. Neural Networks, 2003

UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3".
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003

2002
Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel floating-gate multiple-valued CMOS full-adder.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A novel floating-gate multiple-valued signal to binary signal converter.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Floating-gate CMOS differential analog inverter for ultra low-voltage applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Extreme low-voltage floating-gate CMOS transconductance amplifier.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel low-voltage floating-gate CMOS transconductance amplifier with sinh (tanh) shaped output current.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A 0.3 V floating-gate differential amplifier input stage with tunable gain.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Novel reconfigurable two-MOSFET UV-programmable floating-gate circuits for CARRY, NAND, NOR or INVERT functions.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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