Amandeep Kaur

Orcid: 0000-0003-2056-0884

Affiliations:
  • IIT Delhi, New Delhi, India


According to our database1, Amandeep Kaur authored at least 18 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An Intelligent System With Reduced Readout Power and Lightweight CNN for Vision Applications.
IEEE Trans. Circuits Syst. Video Technol., February, 2024

2023
An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications.
Circuits Syst. Signal Process., 2023

A Single Capacitor-Based Offset Reduction Technique for Energy-Efficient Dynamic Comparators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A Multiplying Digital to Analog Converter Insensitive to Component Mismatch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An input folding high speed cyclic ADC for column-parallel readout in CMOS image sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

AI driven Wide Dynamic Range CMOS Image Sensor.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients.
IEEE Trans. Circuits Syst. Video Technol., 2021

A low kickback noise and low power dynamic comparator.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

CMOS image sensor with adaptive readout scheme for low power applications.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A High Speed, Low Energy Comparator Based on Current Recycling Approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

On-chip Pixel Reconstruction using Simple CNN for Sparsely Read CMOS Image Sensor.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
A CMOS Image Sensor with Column-Parallel Cyclic-SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A reconfigurable cyclic ADC for biomedical applications.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An On-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2017
A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs.
Proceedings of the International SoC Design Conference, 2017

2016
A low power low latency comparator for ramp ADC in CMOS imagers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016


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